Senior RFIC Layout Designer for Space & Defense Tech

Future Ventures; Hawthorne (CA); On-site; USD 140,000 - 205,000; Full time

Benefits offered by this job

Stock options

Medical, vision & dental insurance

401(k) retirement plan

Paid vacation

Paid holidays

Paid sick leave

Job summary

SpaceX in Hawthorne, CA is seeking a Sr. RFIC Layout Designer for the Starshield Silicon program.

You will lead the layout discipline for RF and analog blocks across advanced nodes, collaborating with IC design and packaging teams to optimize floor plans, parasitics, and reliability for space and ground systems. Candidates have 5+ years in IC layout and strong analog layout skills, with experience in 16/7/5nm nodes, RF blocks, and scripting for layout processes.

Qualifications

• Bachelor’s degree in electrical or computer engineering or 8+ years of professional experience with IC layout in lieu of a degree.
• 5+ years of professional experience as an IC layout designer.
• Experience with advanced node IC layouts (16nm/7nm/5nm or below).
• Experience with RF blocks (LNA, VCOs, mixers) and high-frequency designs.
• Strong analog layout skills and parasitic minimization.

Responsibilities

• Determine chip floor plan and power/ground strategy; coordinate with packaging for pad locations.
• Estimate layout schedule and identify complex areas for early investigation.
• Layout of custom RF and analog blocks with attention to matching and parasitics.
• Design rule checks, electrical rule checks, and LVS; resolve errors.
• Top-level layout integration with ESD structures and pad assembly; tape-out readiness.

Skills

Analog layout

Advanced nodes

RF circuit layout

Low-noise amplifiers

VCOs & mixers

Scripting (Python/Perl/Shell)

Revision control

Circuit design

Device matching & noise isolation

Linux

Communication skills

Independent problem solving

Education

Bachelor’s degree in electrical or computer engineering

Tools

Linux

Job description

SpaceX in Hawthorne, CA is seeking a Sr. RFIC Layout Designer for the Starshield Silicon program.

You will lead the layout discipline for RF and analog blocks across advanced nodes, collaborating with IC design and packaging teams to optimize floor plans, parasitics, and reliability for space and ground systems. Candidates have 5+ years in IC layout and strong analog layout skills, with experience in 16/7/5nm nodes, RF blocks, and scripting for layout processes.