RFIC Layout Engineer for Space & Defense Silicon

SpaceX; Hawthorne (CA); On-site; USD 105,000 - 150,000; Full time

Benefits offered by this job

Stock options

401(k) retirement plan

Paid vacation and holidays

Job summary

SpaceX is seeking an RFIC Layout Designer for the Starshield Silicon program. The role focuses on full‑chip RF/analog layout, matching and parasitics, with interactions across systems architecture, ASIC design, firmware, and post‑silicon validation.

Responsibilities include floor planning, schedule estimation, DRC/ER/LVS checks, and tape-out readiness. Ideal candidates have strong analog layout skills and experience with advanced nodes and high-frequency RF blocks.

Qualifications

• Bachelor’s degree in electrical or computer engineering or 3+ years of professional experience with IC layout.
• 1+ years of professional experience as an IC layout designer.

Responsibilities

• Determine the chip floor plan including power/ground distribution and pads.
• Estimate the schedule for the layout work and identify complex areas.
• Layout of RF and analog blocks with focus on matching and minimizing parasitic capacitance.
• Perform DRC, ERC and LVS checks and resolve errors.
• Coordinate top-level layout with ESD structures and pad assembly; prepare tape-out.
• Collaborate with EDA vendors to trial new tools and features.
• Create guides and demos to showcase layout techniques.

Skills

Analog layout

RFIC layout

Linux

Python scripting

Version control

Communication skills

Independent problem solving

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

EDA tools

Shell scripting

Perl

Python

Job description

SpaceX is seeking an RFIC Layout Designer for the Starshield Silicon program. The role focuses on full‑chip RF/analog layout, matching and parasitics, with interactions across systems architecture, ASIC design, firmware, and post‑silicon validation.

Responsibilities include floor planning, schedule estimation, DRC/ER/LVS checks, and tape-out readiness. Ideal candidates have strong analog layout skills and experience with advanced nodes and high-frequency RF blocks.