Senior/Principal Physical Design Engineer (remote)

Chelsea Search Group; Portland (OR); Remote; USD 180,000 - 260,000; Full time

Job summary

Chelsea Search Group seeks a Senior/Principal Physical Design Engineer (remote) to drive ASIC physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure. You will work with RTL, verification, DFT, and analog teams to deliver high-performance silicon using Fusion Compiler and Calibre.

Ideal candidates have 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog, and a proven record of first-pass success.

Qualifications

• 10+ years of ASIC/SoC design experience.
• Strong RTL and digital IC design fundamentals.
• Proficient in Verilog/SystemVerilog.
• Experience with industry standard tools and methodologies.
• Willingness to mentor junior engineers.
• Familiarity with RISC architectures is a plus.

Responsibilities

• Analyze and optimize designs to meet PPA and timing targets.
• Collaborate with RTL, verification, DFT and analog teams.
• Develop and optimize floorplans with high-speed interfaces.
• Develop and improve physical design flows and automation.
• Identify and resolve congestion, timing, and routing issues.
• Participate in reviews and provide design recommendations.
• Perform full-chip physical design from RTL to GDSII.
• Perform physical verification and signoff with Calibre.
• Drive timing closure across modes and process corners.
• Mentor engineers and contribute to internal capabilities.

Skills

RTL design

Verilog/SystemVerilog

Digital IC design

Problem solving

Leadership

Mentoring

Education

BSEE/MSEE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

EDA tools

Job description

Senior/Principal Physical Design Engineer (remote)

• Portland, OR

Job Description

We are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. You'll own critical aspects of physical implementation, including floorplanning, placement, CTS, routing, timing closure, and PPA optimization, working with advanced technologies such as RISC-V, DDR, and SerDes. Using industry-leading tools including Synopsys Fusion Compiler and Siemens Calibre, you'll solve challenging physical design problems and help drive successful silicon outcomes. This is an opportunity to make a significant technical impact while collaborating with a highly experienced, multidisciplinary ASIC engineering team.

Essential Duties and Qualifications

• Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
• Collaborate closely with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure successful chip integration.
• Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.
• Develop, maintain, and improve physical design flows, scripts, methodologies, and automation to increase efficiency and design quality.
• Identify and resolve congestion, routing, timing, power integrity, and physical verification issues throughout the implementation process.
• Participate in design reviews and provide recommendations regarding floorplanning, physical architecture, implementation strategy, and PPA tradeoffs.
• Perform full-chip physical design implementation from synthesized netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure.
• Perform physical verification and signoff activities using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.
• Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints.
• Provide technical guidance and mentoring to other engineers and contribute to the continued development of the team's internal physical design capabilities.
• Support final design signoff and tapeout, ensuring all applicable physical design and verification requirements have been satisfied.
• Support integration and physical implementation of third-party and internally developed IP blocks.
• Support the physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.
• Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.
• Utilize Synopsys Fusion Compiler for physical implementation, optimization, and design closure.

Qualifications

• 10+ years of direct industry experience with ASIC and/or SoC design.
• BSEE/MSEE or equivalent
• Excellent problem-solving skills and attention to detail.
• Experience with industry standard development tools and methodologies.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Proven track record of first-pass successes.
• Self-starter with the ability to assume leadership roles.
• Strong background in RTL based digital IC design using Verilog/SystemVerilog
• Strong understanding of digital design principles.
• Willingness to mentor and develop less experienced engineers.