Senior/Principal Physical Design Engineer (remote)

Chelsea Search Group; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

Chelsea Search Group is seeking an experienced Senior/Principal Physical Design Engineer to lead complex ASIC/SoC implementations from RTL to GDSII. You will own floorplanning, placement, CTS, routing, timing closure, and PPA optimization using leading tools like Fusion Compiler and Calibre.

collaboration with RTL, DFT, analog/mixed-signal teams is required. Responsibilities include developing PD flows, resolving congestion and timing issues, and guiding junior engineers while supporting tapeout

Qualifications

• Minimum 10+ years of direct ASIC/SoC experience.
• BSEE/MSEE or equivalent required.
• Excellent problem-solving and attention to detail.
• Experience with industry standard EDA tools and methodologies.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proven track record of first-pass successes and leadership.

Responsibilities

• Analyze and optimize designs to meet power, performance, and area objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
• Collaborate with RTL design, verification, DFT, analog/mixed-signal, packaging, and other teams to ensure chip integration.
• Develop and optimize floorplans with complex IP and high-speed interfaces such as DDR and SerDes.
• Maintain and improve physical design flows, scripts, and automation to boost efficiency and quality.
• Identify and resolve congestion, routing, timing, power integrity, and PV issues during implementation.
• Participate in design reviews and provide guidance on floorplanning, architecture, and PPA tradeoffs.
• Perform full-chip physical design from netlist to GDSII including CTS and routing for timing closure.
• Conduct physical verification using Calibre (DRC/LVS) and resolve violations.
• Lead timing closure across multiple modes and process corners.
• Mentor engineers and contribute to the team’s internal design capabilities.
• Support final signoff and tapeout, ensuring adherence to all PD/verification requirements.
• Support IP integration and third-party IP implementation for RISC-V based subsystems.

Skills

Physical design

P&R engineering

Verilog/SystemVerilog

RTL design

Timing closure

PPA optimization

Floorplanning

Mentoring

Leadership

Education

BSEE/MSEE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

Design Compiler

Job description

Senior/Principal Physical Design Engineer

Job Description:
We are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. Youll own critical aspects of physical implementation, including floorplanning, placement, CTS, routing, timing closure, and PPA optimization, working with advanced technologies such as RISC-V, DDR, and SerDes. Using industry-leading tools including Synopsys Fusion Compiler and Siemens Calibre, youll solve challenging physical design problems and help drive successful silicon outcomes. This is an opportunity to make a significant technical impact while collaborating with a highly experienced, multidisciplinary ASIC engineering team.

Essential Duties and Qualifications:

• Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.


• Collaborate closely with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure successful chip integration.


• Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.


• Develop, maintain, and improve physical design flows, scripts, methodologies, and automation to increase efficiency and design quality.


• Identify and resolve congestion, routing, timing, power integrity, and physical verification issues throughout the implementation process.


• Participate in design reviews and provide recommendations regarding floorplanning, physical architecture, implementation strategy, and PPA tradeoffs.


• Perform full-chip physical design implementation from synthesized netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure.


• Perform physical verification and signoff activities using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.


• Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints.


• Provide technical guidance and mentoring to other engineers and contribute to the continued development of the team's internal physical design capabilities.


• Support final design signoff and tapeout, ensuring all applicable physical design and verification requirements have been satisfied.


• Support integration and physical implementation of third-party and internally developed IP blocks.


• Support the physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.


• Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.


• Utilize Synopsys Fusion Compiler for physical implementation, optimization, and design closure.

Qualifications:

• 10+ years of direct industry experience with ASIC and/or SoC design.


• BSEE/MSEE or equivalent


• Excellent problem-solving skills and attention to detail.


• Experience with industry standard development tools and methodologies.


• Familiarity with RISC architectures (e.g., ARM, MIPS).


• Proficiency in Synopsys Design Compiler and other EDA tools.


• Proven track record of first-pass successes.


• Self-starter with the ability to assume leadership roles.


• Strong background in RTL based digital IC design using Verilog/SystemVerilog


• Strong understanding of digital design principles.


• Willingness to mentor and develop less experienced engineers.

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