Principal ASIC Physical Design Engineer

Chelsea Search Group; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

Chelsea Search Group is seeking an experienced Senior/Principal Physical Design Engineer to lead complex ASIC/SoC implementations from RTL to GDSII. You will own floorplanning, placement, CTS, routing, timing closure, and PPA optimization using leading tools like Fusion Compiler and Calibre.

collaboration with RTL, DFT, analog/mixed-signal teams is required. Responsibilities include developing PD flows, resolving congestion and timing issues, and guiding junior engineers while supporting tapeout

Qualifications

• Minimum 10+ years of direct ASIC/SoC experience.
• BSEE/MSEE or equivalent required.
• Excellent problem-solving and attention to detail.
• Experience with industry standard EDA tools and methodologies.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proven track record of first-pass successes and leadership.

Responsibilities

• Analyze and optimize designs to meet power, performance, and area objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
• Collaborate with RTL design, verification, DFT, analog/mixed-signal, packaging, and other teams to ensure chip integration.
• Develop and optimize floorplans with complex IP and high-speed interfaces such as DDR and SerDes.
• Maintain and improve physical design flows, scripts, and automation to boost efficiency and quality.
• Identify and resolve congestion, routing, timing, power integrity, and PV issues during implementation.
• Participate in design reviews and provide guidance on floorplanning, architecture, and PPA tradeoffs.
• Perform full-chip physical design from netlist to GDSII including CTS and routing for timing closure.
• Conduct physical verification using Calibre (DRC/LVS) and resolve violations.
• Lead timing closure across multiple modes and process corners.
• Mentor engineers and contribute to the team’s internal design capabilities.
• Support final signoff and tapeout, ensuring adherence to all PD/verification requirements.
• Support IP integration and third-party IP implementation for RISC-V based subsystems.

Skills

Physical design

P&R engineering

Verilog/SystemVerilog

RTL design

Timing closure

PPA optimization

Floorplanning

Mentoring

Leadership

Education

BSEE/MSEE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

Design Compiler

Job description

Chelsea Search Group is seeking an experienced Senior/Principal Physical Design Engineer to lead complex ASIC/SoC implementations from RTL to GDSII. You will own floorplanning, placement, CTS, routing, timing closure, and PPA optimization using leading tools like Fusion Compiler and Calibre.

collaboration with RTL, DFT, analog/mixed-signal teams is required. Responsibilities include developing PD flows, resolving congestion and timing issues, and guiding junior engineers while supporting tapeout