Senior Principal DFT Architect – SoC Test & Verification

Cadence Design Systems; Austin (TX); On-site; USD 196,000 - 364,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan

Employee stock purchase plan

Medical/dental/vision

More benefits

Job summary

Cadence Design Systems is seeking a highly motivated hardware engineer to join the Modus R&D team in the Design-For-Test (DFT) IP unit. You will design and implement DFT hardware, test fabrics, and on‑chip test networks for next‑generation SoCs, including LBIST, MBIST, POST and IST capabilities.

You will collaborate across RTL, verification, synthesis, and physical design teams to ensure high‑coverage, low‑cost test strategies while delivering reusable IP and robust test infrastructure.

Qualifications

• Proficient in Verilog/SystemVerilog RTL for digital hardware design.
• Hands-on coding and automation with SystemVerilog/Verilog, plus scripting with Perl and Python
• Mastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive quality
• Knowledge of network structures and method for communicating data across an SoC
• Full‑Flow Development & Integration
• Proven experience developing complex reusable IPs from architecture through delivery
• Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows
• Ability to manage internal and third‑party/services IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking
• Ability to debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments
• Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral
• DFT Architecture – Deep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory‑mapped interfaces, reset/clock architecture, and low‑power design considerations
• Strong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design‑for‑testability tradeoffs
• Knowledge of DFT IP concepts, hardware, and test network communication
• Project Ownership & Team Communication – Experience leading design reviews, architecture reviews, microarchitecture reviews, and implementation readiness reviews
• Strong project execution and project management skills, including planning, dependency tracking, risk management, milestone ownership, and cross‑functional coordination
• Ability to mentor senior and junior engineers and provide technical leadership across teams
• Good communication skills with a development team spread across multiple locations
• Prior experience with large software development projects is highly recommended

Responsibilities

• Design and implement advanced Design‑for‑Test (DFT) hardware, test fabrics, and on‑chip test networks used in next‑generation SoCs.
• Contribute to the hardware and software development of industry‑leading test solutions such as scan compression, hierarchical test access architectures, LBIST, MBIST, POST, and IST.
• Support high‑coverage, low‑cost test strategies across complex semiconductor designs.
• Collaborate with verification teams to drive quality and test coverage across RTL, synthesis, timing, and integration environments.

Skills

RTL Design

SystemVerilog

Perl/Python scripting

UVM

DTF/verification knowledge

SoC data networks

Synthesis/Timing closure

IP integration

Debugging hardware

Documentation

Tools

Xcelium

JasperGold

Genus

Innovus

Tempus

Modus

Job description

Cadence Design Systems is seeking a highly motivated hardware engineer to join the Modus R&D team in the Design-For-Test (DFT) IP unit. You will design and implement DFT hardware, test fabrics, and on‑chip test networks for next‑generation SoCs, including LBIST, MBIST, POST and IST capabilities.

You will collaborate across RTL, verification, synthesis, and physical design teams to ensure high‑coverage, low‑cost test strategies while delivering reusable IP and robust test infrastructure.