Senior DFT Engineer: SoC/ASIC Test Architect

QFocus Technologies LLC; Sunnyvale, Northern (CA, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

QFocus Technologies LLC seeks a Senior DFT Engineer to define, architect, and execute robust Design-for-Test strategies for high-performance SoCs/ASICs. You will collaborate with front-end, physical, verification, and product teams to maximize test coverage and yield.

You will lead DFT architectures (Scan, ATPG, MBIST, JTAG), perform insertion and optimization, and support post-silicon bring-up while ensuring production test readiness and silicon quality.

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
• Proficiency in Verilog/SystemVerilog for DFT integration and simulation debugging.
• Experience with scan insertion, ATPG, MBIST, and JTAG integration.
• Post-silicon support of patterns on target silicon and production yield ramp.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG.
• Perform scan chain insertion, stitching, and optimization for timing closure.
• Integrate MBIST controllers, repair mechanisms, and memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Run Verilog/SystemVerilog simulations for gate-level DFT validation with SDF.
• Conduct DFT linting and rule checks with SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Translate pre-silicon ATPG/MBIST patterns to tester formats (WGL, STIL) for ATE deployment.
• Support post-silicon bring-up and debug first-silicon DFT features.
• Collaborate with Product and Test Engineering to optimize test time and yield.

Skills

Verilog / SystemVerilog

DFT design

ATPG

MBIST

JTAG

Post-Silicon support

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

WGL / STIL

ATE deployment

Job description

QFocus Technologies LLC seeks a Senior DFT Engineer to define, architect, and execute robust Design-for-Test strategies for high-performance SoCs/ASICs. You will collaborate with front-end, physical, verification, and product teams to maximize test coverage and yield.

You will lead DFT architectures (Scan, ATPG, MBIST, JTAG), perform insertion and optimization, and support post-silicon bring-up while ensuring production test readiness and silicon quality.