DFT Design Engineer - SoC Test & MBIST Expert

Cadence Design Systems; Austin (TX); On-site; USD 90,000 - 120,000; Full time

Job summary

Cadence Design Systems is seeking a DFT Design Engineer in Austin, Texas, to engage in digital design focusing on Design for Test (DFT). Applicants must have 2-10 years of relevant experience and be proficient in scan chain insertion, MBIST, and automatic test pattern generation (ATPG).

This role demands collaboration across various teams, problem-solving skills, and the ability to thrive in a fast-paced environment. Knowledge of Cadence tools is a plus, along with a systematic approach to quality metrics-driven work.

Qualifications

• 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT).
• Knowledge of memory built-in self-test (MBIST) and JTAG standards.
• Ability to debug and analyze failures to improve fault coverage.

Responsibilities

• Generate ATPG patterns to achieve design test coverage goals.
• Independently complete DFT tasks while collaborating with cross-functional teams.
• Develop debug and analysis of failures in the testbenches.

Skills

DFT insertion flows

Scan chain insertion

Automatic Test Pattern Generation (ATPG)

Debugging Verilog testbenches

Collaboration in team environment

Tools

Cadence tools

Job description

Cadence Design Systems is seeking a DFT Design Engineer in Austin, Texas, to engage in digital design focusing on Design for Test (DFT). Applicants must have 2-10 years of relevant experience and be proficient in scan chain insertion, MBIST, and automatic test pattern generation (ATPG).

This role demands collaboration across various teams, problem-solving skills, and the ability to thrive in a fast-paced environment. Knowledge of Cadence tools is a plus, along with a systematic approach to quality metrics-driven work.