Principal SoC DFT Engineer

Nokia; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

A leading technology company in California is seeking a Principal DFT Engineer to work on ASIC implementation for their Network Infrastructure Optical Network group. The role involves end-to-end responsibility for DFT insertion and verification, requiring strong experience in DFT methodologies and scripting. Ideal candidates will have significant hands-on experience with EDA tools and a strong focus on achieving first-pass silicon success. Excellent communication skills and attention to detail are essential for this execution-driven position.

Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 8 years of related experience.
• 5+ years of hands-on DFT implementation experience.
• Strong proficiency with EDA tools and TCL scripting.

Responsibilities

• Work on DFT architecture and implementation across various technologies.
• Execute DFT verification and debug errors.
• Collaborate with design teams for DFT-related issues.

Skills

DFT implementation experience

TCL scripting

Debugging skills

Communication skills

Education

Bachelor’s degree or higher in Computer Science/Electrical Engineering

Tools

EDA tools

Industry simulator tools

Job description

Overview

The Principal DFT Engineer will work on cutting‑edge ASIC implementation for the Network Infrastructure Optical Network group

Qualifications

You Have:

• Bachelor’s degree in computer science, Electrical Engineering or related fields and 8 years
  of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 years of experience.
• 5+ years of hands‑on DFT implementation experience
• Strong proficiency with EDA tools, including:
  • Logic BIST insertion and verification
  • MBIST / BISR insertion and verification
  • Boundary Scan (IEEE 1149.x)
  • JTAG and HS Analog/mixed signal IP IOBIST integration
  • ATPG pattern generation and coverage analysis
• Proven ability to resolve DFT DRCs, connectivity issues, and testability problems
• Strong TCL scripting skills for DFT automation and flow execution
• Experience developing and validating scan and test‑mode timing constraints
• End‑to‑end DFT lifecycle experience, from RTL/netlist through silicon debug
• Strong debugging skills, attention to detail, and sense of ownership
• Excellent verbal and written communication skills

Responsibilities

You will be working on DFT architecture and implementation across logic BIST, MBIST, BISR, Boundary Scan, and JTAG. This is a highly execution‑driven role requiring end‑to‑end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post‑silicon debug. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design and product engineers to achieve first‑pass silicon success.

Perform hands‑on DFT implementation and verification, including:

• Logic BIST and scan compression
• MBIST and BISR
• Boundary Scan (IEEE 1149.x) insertion
• JTAG insertion and connectivity
• High‑speed analog/mixed signal IP integration
• Execute DFT verification, debug, and DFT DRC closure
• Identify, debug, and resolve DFT rule violations at both block and top levels
• Run, analyze, and debug DFT/RTL checks, working with design teams to close violations
• Generate, simulate, and debug MBIST and logic ATPG patterns
• Analyze test results and drive test coverage improvement and closure
• Develop and validate DFT timing constraints for scan, BIST, and test modes
• Create and maintain TCL scripts to automate DFT insertion, verification, and analysis flows
• Support hierarchical DFT implementation and resolve integration issues
• Collaborate with RTL and Physical Design teams to address DFT‑related design issues
• Support pre‑silicon DFT signoff and assist with post‑silicon pattern bring‑up and debug
• Assist with ATE pattern conversion and debug as needed

Experience with gate‑level simulations and debugging with industry simulator tools.