DFT (Design for Test) Lead

BayOne Solutions; United States; Remote; USD 140,000 - 190,000; Full time

Job summary

BayOne Solutions seeks a DFT Lead to drive design-for-test features across advanced silicon, coordinating with RTL, test engineers and fabrication teams in a remote, full-time role.

You will implement scan, mbist, boundary scan and BISR, develop DFT IP, and lead post-silicon debug efforts with limited mentorship.

Requires 8–10 years in electrical/computer engineering, strong JTAG, ATPG, and experience with Tessent, Xcelium, Genus and TempPrimetime.

Qualifications

• Must have 8–10 years of experience in electrical or computer engineering.
• Proficient with JTAG, scan and BIST architectures including memory BIST and boundary scan.
• Experience integrating 3rd party IPs and high-speed digital/analog macros.
• Hands-on post-silicon debugging of DFT patterns (scan/mbist/boundary scan).

Responsibilities

• Implement Hardware DFT features—scan, mbist, BISR, boundary scan, and DFT simulations debugging.
• Develop innovative DFT IP and coordinate full chip design integration with RTL testability features.
• Collaborate with multi-functional teams to drive testability for new silicon device models (bare/stacked dies).
• Craft solutions and debug with minimal mentorship.

Skills

JTAG protocols

Scan architectures

BIST architectures

Memory BIST

Boundary scan

3rd party IP integration

High-speed macros

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Tessent

Xcelium

Genus

TempPrimetime

Job description

Job Title: DFT (Design for Test) Lead

Location: (Remote)

Shift: 9am -- 5pm PST

Duration: 12 Months

Contract Role on W2

Job Responsibilities:

• Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Requirements: ("Must have" Qualifications)

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP's and high-speed digital/analog macros
• Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, TempPrimetime
• At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production

Desired Skills/Qualifications/System Experience requirements: ("Nice to have" Qualifications)

• Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production
• Ability to quickly learn new concepts and adapt to evolving technologies
• Excellent communication and presentation skills
• Strong attention to detail and system level understanding of networking and photonic solutions.