Senior Principal DFT Architect for SoC Test & Verification

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 140,000 - 240,000; Full time

Job summary

Cadence Design Systems, Inc. in Austin, TX seeks a highly motivated hardware engineer to join the DFT IP team.

You will design and implement DFT hardware, test fabrics, and on‑chip networks for next-generation SoCs, contributing to high-coverage, low-cost test strategies across complex designs. The role requires strong RTL/Verilog/SystemVerilog skills, UVM verification, and experience with synthesis, timing, and IP integration.

Qualifications

• Strong RTL design & verification experience in digital hardware.
• Verilog/SystemVerilog RTL coding and simulation expertise.
• Hands-on coding with SystemVerilog/Verilog; scripting in Perl/Python.
• Mastery of UVM and directed testbench verification, test planning, coverage closure.
• Knowledge of data communication across SoCs and DFT requirements.
• Experience with full-flow development, timing closure, and signoff workflows.
• Ability to lead design reviews and mentor engineers.
• Excellent cross-functional communication across locations.

Responsibilities

• Design and implement advanced DFT hardware and on-chip test networks for Next‑Gen SoCs.
• Develop test fabrics and IST/MBIST/LBIST/POST components and integrate with IP.
• Lead verification planning, ensure coverage closure, and drive quality with teams.
• Mentor engineers and drive architecture/interface decisions across RTL, verification, and physical design.
• Collaborate with CAD and software teams to ensure scalable, reusable IP.

Skills

RTL Design & Verification

Verilog/SystemVerilog

Scripting (Perl, Python)

UVM & testbench

IP integration & verification

DTF/DFT test concepts

Chips/SoC architectures

Project ownership

Debug across RTL/verify/synthesis

Tools

Xcelium

Genus

Innovus

JasperGold

Cadence signoff tools

Job description

Cadence Design Systems, Inc. in Austin, TX seeks a highly motivated hardware engineer to join the DFT IP team.

You will design and implement DFT hardware, test fabrics, and on‑chip networks for next-generation SoCs, contributing to high-coverage, low-cost test strategies across complex designs. The role requires strong RTL/Verilog/SystemVerilog skills, UVM verification, and experience with synthesis, timing, and IP integration.