DFT Design Engineer: SoC/ASIC Test & MBIST Expert

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Cadence Design Systems, Inc. in Austin seeks an SoC/ASIC Digital Design Engineer with DFT expertise to drive test methodologies, including scan chain insertion, MBIST and ATPG.

The role requires hands-on experience with Verilog testbenches and debugging complex test failures, plus knowledge of JTAG/IEEE test standards and collaboration across Architecture, Design and Customer teams. The position emphasizes independent DFT task execution, a fast-paced project environment, and the use of Cadence

Qualifications

• 2-10 years of SoC/ASIC Digital Design with focus on DFT.
• Intimate knowledge of DFT insertion flows.
• Basic scan chain insertion using synthesis or other software tools.
• Experience in compression scan insertion, LBIST and other scan technologies.
• MBIST expertise.
• ATPG to meet design test coverage goals.
• Debug and analysis of failures to improve fault coverage.
• Verification of ATPG testbenches and debugging root cause of simulations.

Skills

DFT

Scan chain insertion

MBIST

ATPG

Verilog testbenches

JTAG 1149.1/6

IEEE1500

IEEE1687

Cadence tools

Tools

Cadence tools

Job description

Cadence Design Systems, Inc. in Austin seeks an SoC/ASIC Digital Design Engineer with DFT expertise to drive test methodologies, including scan chain insertion, MBIST and ATPG.

The role requires hands-on experience with Verilog testbenches and debugging complex test failures, plus knowledge of JTAG/IEEE test standards and collaboration across Architecture, Design and Customer teams. The position emphasizes independent DFT task execution, a fast-paced project environment, and the use of Cadence