DFT Design Engineer for SoC RTL & Test Innovation

Intel; Austin (TX); On-site; USD 141,910 - 200,340; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Paid time off

Job summary

Intel's Austin campus seeks a DFT Design Engineer to shape silicon solutions by integrating DFT into cutting-edge SoCs and IPs. You will collaborate with architecture, design, verification, and manufacturing teams to drive innovation and optimize test coverage, power, performance, and area.

You will develop RTL/structural code for DFT features such as SCAN, MBIST, and BSCAN, provide timing closure, and support IP/SoC integration.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering.
• 5+ years in DFT/SoC design or related semiconductor areas.
• Experience with RTL design using Verilog/VHDL/SystemVerilog.

Responsibilities

• Develop RTL/structural code for DFT features (SCAN, MBIST, BSCAN).
• Provide timing closure support and test content generation for manufacturing.
• Collaborate on architecture/microarchitecture definitions for blocks/SoCs under DFT.
• Drive high test coverage and optimize power, performance, and area.
• Support IP/SoC integration and develop HVM content for ATE.

Skills

DFT concepts

RTL design

Verilog/SV

Python scripting

Cross-functional collaboration

Education

Bachelor's degree in EE/CE

Tools

Tessent

DFT Compiler

Modus

ISTK

Job description

Intel's Austin campus seeks a DFT Design Engineer to shape silicon solutions by integrating DFT into cutting-edge SoCs and IPs. You will collaborate with architecture, design, verification, and manufacturing teams to drive innovation and optimize test coverage, power, performance, and area.

You will develop RTL/structural code for DFT features such as SCAN, MBIST, and BSCAN, provide timing closure, and support IP/SoC integration.