Senior Principal AI ASIC Design Engineer

Black Sesame Technologies Inc; San Jose (CA); On-site; USD 230,000 - 300,000; Full time

Job summary

Black Sesame Technologies Inc. is seeking a Senior Principal ASIC Design Engineer in the United States.

You will define microarchitecture and lead RTL implementation for next-generation AI compute engines, driving timing closure and cross-functional collaboration with architecture, verification, and physical design teams. You will guide power, performance, and area optimizations while mentoring engineers and ensuring RTL quality and sign-off across the project lifecycle.

Qualifications

• BS/MS in Electrical or Computer Engineering or related field.
• ASIC/SoC design ownership from microarchitecture to RTL sign-off.
• Strong SystemVerilog/Verilog with synthesizable coding experience.
• Experience with timing closure, PVT corners, and performance/power/area optimization.
• Demonstrated technical leadership and cross-functional collaboration.
• Scripting in Python, Shell, or TCL for EDA automation and analysis.

Responsibilities

• Define microarchitecture and lead RTL implementation for high-efficiency AI compute engines.
• Drive timing closure by analyzing Setup/Hold, clocking, and critical-path issues across PVT corners.
• Lead power and area optimization using clock gating, operand isolation, and architectural tradeoffs.
• Own RTL quality and sign-off activities, including lint, CDC, RDC, synthesis, and timing constraints.
• Mentor engineers and collaborate with architecture, verification, and physical design teams.

Skills

Microarchitecture definition

RTL design leadership

Timing analysis

Power and area optimization

RTL sign-off

Technical leadership

Scripting (Python/TCL)

SystemVerilog/Verilog

Education

BS/MS in Electrical or Computer Engineering

Tools

EDA tools

Synthesis/CDC/RDC checks

Job description

Black Sesame Technologies Inc. is seeking a Senior Principal ASIC Design Engineer in the United States.

You will define microarchitecture and lead RTL implementation for next-generation AI compute engines, driving timing closure and cross-functional collaboration with architecture, verification, and physical design teams. You will guide power, performance, and area optimizations while mentoring engineers and ensuring RTL quality and sign-off across the project lifecycle.