Senior AI ASIC Design Engineer — Lead High-Perf SoCs

Positron AI; United States; Hybrid; USD 200,000 - 300,000; Full time

Benefits offered by this job

Competitive salary

Equity

Flexible work environment

Comprehensive benefits

Job summary

Positron AI in the United States is seeking a Senior ASIC Design Engineer to lead the microarchitecture and RTL delivery of high-performance inference silicon.

You will mentor junior engineers, collaborate across architecture, verification and physical design, and own PPA tradeoffs to meet ambitious schedules while advancing interconnects and memory interfaces.

Gain influence over design reviews, signoff, and collaborative workflows in a fast-growing hardware AI company.

Qualifications

• 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
• Proven track record from spec -> microarchitecture -> RTL -> signoff with strong PPA outcomes.
• Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
• Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.

Responsibilities

• Define microarchitecture for complex IP blocks and subsystems.
• Deliver production-quality SystemVerilog RTL with clear interfaces.
• Lead lint, CDC/RDC, DFT integration and timing closure.
• Architect and integrate high-speed memory interfaces (HBM/DDR).
• Mentor junior engineers and drive design reviews.

Skills

SystemVerilog RTL

Microarchitecture

RTL signoff

Leadership

EDA tools

PCIe/AMBA

High-performance datapaths

Education

BS/MS in EE/CE

Tools

EDA tool suites

Lint tools

DFT tooling

Synthesis/STA

Cocotb/UVM

Job description

Positron AI in the United States is seeking a Senior ASIC Design Engineer to lead the microarchitecture and RTL delivery of high-performance inference silicon.

You will mentor junior engineers, collaborate across architecture, verification and physical design, and own PPA tradeoffs to meet ambitious schedules while advancing interconnects and memory interfaces.

Gain influence over design reviews, signoff, and collaborative workflows in a fast-growing hardware AI company.