Senior Principal Digital Design

Black Sesame Technologies Inc; San Jose (CA); On-site; USD 230,000 - 300,000; Full time

Job summary

Black Sesame Technologies Inc. is seeking a Senior Principal ASIC Design Engineer in the United States.

You will define microarchitecture and lead RTL implementation for next-generation AI compute engines, driving timing closure and cross-functional collaboration with architecture, verification, and physical design teams. You will guide power, performance, and area optimizations while mentoring engineers and ensuring RTL quality and sign-off across the project lifecycle.

Qualifications

• BS/MS in Electrical or Computer Engineering or related field.
• ASIC/SoC design ownership from microarchitecture to RTL sign-off.
• Strong SystemVerilog/Verilog with synthesizable coding experience.
• Experience with timing closure, PVT corners, and performance/power/area optimization.
• Demonstrated technical leadership and cross-functional collaboration.
• Scripting in Python, Shell, or TCL for EDA automation and analysis.

Responsibilities

• Define microarchitecture and lead RTL implementation for high-efficiency AI compute engines.
• Drive timing closure by analyzing Setup/Hold, clocking, and critical-path issues across PVT corners.
• Lead power and area optimization using clock gating, operand isolation, and architectural tradeoffs.
• Own RTL quality and sign-off activities, including lint, CDC, RDC, synthesis, and timing constraints.
• Mentor engineers and collaborate with architecture, verification, and physical design teams.

Skills

Microarchitecture definition

RTL design leadership

Timing analysis

Power and area optimization

RTL sign-off

Technical leadership

Scripting (Python/TCL)

SystemVerilog/Verilog

Education

BS/MS in Electrical or Computer Engineering

Tools

EDA tools

Synthesis/CDC/RDC checks

Job description

Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading AI SoC provider. Our mass-produced AI chips are already deployed in the Automotive and Robotics markets, delivering high-performance, automotive-grade compute solutions at scale. As we define our next-generation AI inference accelerators, we are rapidly expanding our new Singapore R&D site as well as US R&D site. Join us to build the future of intelligent machines from the ground up.

Job Description: Senior Principal ASIC Design Engineer

In this role, you will serve as a hands-on technical leader designing our next-generation AI compute engines. You will define microarchitecture, lead complex RTL implementation, and solve fundamental hardware challenges required for high-performance AI silicon. You will drive high-speed datapath optimization while ensuring the design meets aggressive timing, power, and area targets.

Responsibilities

• Architecture & RTL Design: Define microarchitecture and lead the implementation of high-efficiency AI ALU, vector, and datapath modules using SystemVerilog/Verilog.
• STA & Timing: Drive timing closure by analyzing and resolving complex Setup/Hold, clocking, and critical-path issues across PVT corners.
• Low Power & PPA: Lead performance, power, and area optimization using techniques such as clock gating, operand isolation, and architectural tradeoff analysis.
• Design Sign-off: Own RTL quality and sign-off activities, including Lint, CDC, RDC, synthesis, timing constraints, and formal or equivalence checks.
• Technical Leadership: Collaborate with architecture, verification, and physical design teams while mentoring engineers and leading complex technical reviews.

Basic Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or a related field.
• ASIC Design Expertise: Extensive experience owning complex ASIC or SoC blocks from microarchitecture through RTL sign-off.
• Timing & PPA: Deep understanding of STA, Setup/Hold, Skew/Jitter, PVT corners, and performance, power, and area optimization.
• HDL Proficiency: Expert-level SystemVerilog/Verilog skills with strong synthesizable coding and hardware-oriented design experience.
• Digital Architecture: Strong knowledge of pipelining, stalling, bypass logic, flow control, and high-performance datapath design.
• Technical Leadership: Demonstrated ability to lead cross-functional technical decisions, mentor engineers, and drive complex designs to completion.
• Scripting: Proficiency in Python, Shell, or TCL for EDA automation and design analysis.

You would be a "Star Candidate" if you have:

• AI Accelerator Experience: Experience designing NPUs, GPUs, vector processors, matrix engines, or other AI compute hardware.
• Computer Arithmetic: Deep knowledge of fixed-point, IEEE-754, FP16, BF16, FP8, or related hardware arithmetic.
• Advanced ASIC Flow: Experience with synthesis, physical design, advanced CDC, low-power design, and silicon bring-up.
• RISC-V Exposure: Experience with RISC-V ISA, vector extensions, execution pipelines, or processor microarchitecture.