Senior Design Verification Engineer

Black Sesame Technologies Inc; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Black Sesame Technologies is seeking a seasoned verification engineer to join our ASIC/IP verification team. You will closely work with designers and architects to plan verification, drive verification environment architecture, and take ownership of key features in production silicon.

You will develop test plans, create test cases, run regressions, and contribute to coverage closure, mentoring junior engineers and pursuing leadership opportunities as responsibilities grow.

Qualifications

• 5+ years of experience in IP and/or SoC verification with successful completion of multiple ASICs in production.
• Solid understanding of SystemVerilog constructs, UVM, and C++ is required.
• Experience writing scripts in Perl or Python; good knowledge of Makefile is a plus.

Responsibilities

• Closely work with designers and architect to come up with verification and execution plans
• Influence and drive verification environment architecture with a team of engineers
• Participate in verification of a complex IP block, take ownership of some of the key features
• Work on test plans, test case development, regression and coverage closure
• Guide and mentor junior engineers as required
• Desire and enthusiasm to grow into leadership role taking progressive responsibility over time

Skills

SystemVerilog

UVM

C++

Python

Perl

Makefile

Verification techniques

Regression management

CPU/GPU/NPU architectures

Tools

Makefile

Job description

Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading AI SoC provider. Our mass-produced AI chips are already deployed in the Automotive and Robotics markets, delivering high-performance, automotive-grade compute solutions at scale. As we define our next-generation AI inference accelerators, we are rapidly expanding our new Singapore R&D site. Join us to build the future of intelligent machines from the ground up.

Responsibilities

• Closely work with designers and architect to come up with verification and execution plans
• Influence and drive verification environment architecture with a team of engineers
• Participate in verification of a complex IP block, take ownership of some of the key features
• Work on test plans, test case development, regression and coverage closure
• Guide and mentor junior engineers as required
• Desire and enthusiasm to grow into leadership role taking progressive responsibility over time

Qualifications

• At least 5 years of experience focused on IP and/or SOC verification with successful completion of multiple ASICs that are in production
• Ability to understand existing verification infrastructure, and execute projects based on those, at the same time influence improvements in existing flows/infrastructure
• Solid understanding of System Verilog constructs, UVM, and C++ is required
• Experience writing scripts in Perl or Python, good knowledge in Makefile is a plus
• Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification
• Good understanding of code and functional coverage, ability to influence coverage improvement with design and verification teams
• Experience and ability to influence regression management tools and processes
• Knowledge of or experience with advanced processor architectures (CPU, GPU, NPU/AI accelerators) and their verification methodologies is a strong plus.