Principal Engineer, Hardware Design (AI2518)

SiMa.ai, Inc.; San Jose (CA); On-site; USD 204,000 - 316,000; Full time

Benefits offered by this job

Private company equity

On-site in San Jose

Comprehensive benefits

Job summary

SiMa.ai, Inc. in San Jose, CA is seeking a Principal ASIC Design Engineer to own complex RTL blocks from concept through silicon bring-up.

The role emphasizes hands-on Verilog/SystemVerilog, block-level optimization, and collaboration with verification, physical design, and firmware teams in a fast-paced startup environment. You will drive ground-up design, timing closure, and DFT readiness while focusing on power, performance, and area targets.

Qualifications

• Requires a Master’s degree in Electrical/Computer Engineering or related field.
• 10+ years of ASIC design experience with block-level RTL and silicon development.
• Expert RTL design skills (Verilog/SystemVerilog), with synthesis, timing closure and DFT.
• Strong microarchitecture trade-off skills and block-level optimization for power, performance, and area.

Responsibilities

• Own microarchitecture definition and RTL implementation of complex blocks from concept through silicon.
• Drive ground-up block design from specification to RTL, integration, and bring-up.
• Develop synthesizable RTL with custom logic, protocol adaptation, and data-path optimizations.
• Define block interfaces and architectural trade-offs; ensure blocks meet timing, power, and area targets.
• Collaborate with verification, physical design, architecture, and firmware teams to validate blocks.
• Drive block-level synthesis, timing closure, and DFT readiness.

Skills

RTL design

Verilog/SystemVerilog

DFT concepts

Timing closure

Power, performance, area optimization

Post-silicon validation

Education

Master's degree in Electrical/Computer Engineering or related field

Tools

PCIe

UCIe

Lab equipment (oscilloscopes, logic analyzers)

Job description

Job Title: Principal Engineer, Hardware Design

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2518

Job Description:

We are seeking a Principal ASIC Design Engineer with deep expertise in RTL design and ground-up block-level silicon development. The ideal candidate will own complex design blocks from microarchitecture and RTL implementation through verification support and silicon bring-up. This position offers the opportunity to shape and influence the design architecture and methodology of SiMa's silicon in a fast-paced startup environment.

Areas of Focus:

• Own microarchitecture definition and RTL implementation of complex blocks from concept through silicon.
• Drive ground-up block design, owning each block from specification and microarchitecture to RTL, integration, and bring-up.
• Develop high-quality, synthesizable RTL (Verilog/SystemVerilog), including custom logic, protocol adaptation, and data-path optimizations.
• Define block-level interfaces, microarchitectural trade-offs, and design specifications.
• Collaborate with verification, physical design, architecture, and firmware teams to ensure each block meets functional, timing, power, and area targets.
• Drive block-level synthesis, timing closure, and DFT readiness.

Key Requirements:

• Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC design, with a strong focus on block-level RTL design and silicon development.
• Proven track record of ground-up block design, taking blocks from microarchitecture and RTL through to working silicon.
• Expert-level RTL design skills (Verilog/SystemVerilog), with hands-on experience in synthesis, timing closure, and DFT concepts.
• Strong understanding of microarchitecture trade-offs, data-path and control logic design, and block-level optimization for power, performance, and area.
• Experience with post-silicon validation and debug, using lab equipment such as oscilloscopes, logic analyzers, and protocol analyzers.

Nice to Have:

• Experience designing hardware for machine learning / AI accelerators.
• Experience integrating blocks into larger SoCs.
• Experience implementing or integrating high-speed interfaces such as PCIe and UCIe.
• Exposure to firmware or driver development for high-speed interfaces.

Personal attributes:

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

The annual salary for this position ranges from $203,800 - $315,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.