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Upscale, Inc. is building high-performance infrastructure for AI workloads. We seek an experienced ASIC design engineer to define micro-architecture for next-gen designs, and to drive power, performance, and area targets.
You will own RTL entry and collaborate across verification, layout, and DFT teams to ensure robust designs. The role demands SystemVerilog expertise, strong fundamentals in logic design, and proven ability to deliver in a fast-paced startup environment.
Upscale, Inc. is building high-performance infrastructure for AI workloads. We seek an experienced ASIC design engineer to define micro-architecture for next-gen designs, and to drive power, performance, and area targets.
You will own RTL entry and collaborate across verification, layout, and DFT teams to ensure robust designs. The role demands SystemVerilog expertise, strong fundamentals in logic design, and proven ability to deliver in a fast-paced startup environment.