Principal ASIC Design Engineer for AI Infrastructure

Upscale, Inc.; Kentucky; On-site; USD 250,000 - 265,000; Full time

Job summary

Upscale, Inc. is hiring an experienced ASIC Design engineer to define micro-architecture for next-generation ASICs and develop RTL that meets timing, power, and area goals.

You will collaborate with verification, emulation, and physical design teams to ensure successful tapeouts. The role requires deep SystemVerilog expertise, five-plus years of ASIC logic design experience, and the ability to thrive in a fast-paced startup setting in Kentucky, USA.

Qualifications

• BS or MS in EE, CE, or CS required.
• 5+ years in ASIC logic design.
• SystemVerilog expertise.

Responsibilities

• Define and document micro-architecture on next generation ASIC designs.
• Design RTL that meets power, performance, and area targets.
• Collaborate with verification and emulation to ensure test plans meet design intent.
• Collaborate with physical design for timing closure and area optimization.
• Work with the DFT team to integrate DFT logic.
• Communicate effectively and work independently within cross-functional teams.

Skills

SystemVerilog

Logic design

Team collaboration

Startup environment

Education

BE/MS in EE/CE/CS

Tools

LINT

CDC

RDC

Job description

Upscale, Inc. is hiring an experienced ASIC Design engineer to define micro-architecture for next-generation ASICs and develop RTL that meets timing, power, and area goals.

You will collaborate with verification, emulation, and physical design teams to ensure successful tapeouts. The role requires deep SystemVerilog expertise, five-plus years of ASIC logic design experience, and the ability to thrive in a fast-paced startup setting in Kentucky, USA.