Principal ASIC Design Engineer

Cognichip; Redwood City (CA); On-site; USD 160,000 - 210,000; Full time

Benefits offered by this job

Competitive compensation

Equity and benefits

Flexible work environment

Job summary

Cognichip is looking for a Principal ASIC Design Engineer in Redwood City, California. This role is vital for integrating AI into chip design, requiring over 15 years of experience in chip and physical design.

The ideal candidate should have expertise in Digital IC and SystemVerilog, with a strong background in AI/ML systems. Competitive compensation and a collaborative environment are offered, reflecting our commitment to pushing boundaries in semiconductor design.

Qualifications

• 15+ years of hands-on experience in Chip Design and Physical Design.
• Proven expertise in Digital IC, ASIC, or SoC design.
• Strong proficiency in SystemVerilog RTL and STA.

Responsibilities

• Translate chip-design expertise into reusable, AI-consumable knowledge bases.
• Identify bottlenecks in the advanced chip design process.
• Define EDA tool usage strategies for AI-native workflows.

Skills

Chip Design and Physical Design

Digital IC

SystemVerilog RTL

STA

Design tradeoffs articulation

Python proficiency

Job description

About Us

At Cognichip, we are building the next-generation AI-enabled solutions to empower semiconductor design engineers with a 10x productivity boost through specialized generative models, agentic workflows and seamless integration with high-performance EDA engines.

Job Title

Principal ASIC Design Engineer

Role Overview

We are seeking a Principal ASIC Design Engineer at the intersection of silicon design and artificial intelligence. This senior IC role focuses on re-imagining chip design flows with an AI-first mindset, and charting the path to incorporate enterprise and know-how into intelligent systems for AI-native production-quality chip design and verification. The ideal candidate combines deep silicon expertise, microarchitecture, RTL, DV, and EDA workflows, into structured AI-driven and tool-aware processes.

Key Responsibilities

• Translate chip-design expertise (RTL/DV best practices, micro-architectural patterns, failure modes) into reusable, AI-consumable knowledge bases and agent playbooks.
• Identify bottlenecks in advanced chip design process and devise novel models, tools, and to rethink workflows to drastically change the outcome.
• Define EDA tool usage strategies and wrappers for AI-native workflows.
• Define evaluation strategies suitable for AI systems to enhance performance and grounding.

Required Qualifications

• 15+ years of hands‑on experience in Chip Design and Physical Design.
• Proven expertise in Digital IC, ASIC, or SoC design; strong proficiency in SystemVerilog RTL and STA.
• Solid understanding of microarchitecture concepts: pipelines, FIFOs, DMA engines, caches, and on‑chip interconnects.
• Deep familiarity with the full design cycle: lint, CDC/RDC, functional simulation, and STA.
• Ability to articulate design tradeoffs and debug complex RTL issues.
• Proficiency in Python; experience integrating tools into automated workflows.

Preferred Qualifications

• Demonstrated experience with AI/ML systems (of any kind), prompt and context engineering.
• Ability to translate complex silicon design problems into structured, executable and verifiable components in agent workflows.
• Experience with AI‑assisted EDA tools or ML/chip design research.
• Contributions to open‑source chip design, EDA tooling, or AI/ML infrastructure.

What We Offer

• A foundational role in how AI transforms chip design.
• A collaborative environment where deep silicon expertise meets cutting‑edge AI research.
• Competitive compensation, equity, and benefits.
• Flexible work with access to world‑class compute and EDA infrastructure.

We are an equal opportunity employer committed to building a diverse and inclusive team.