Senior Principal NPU Architect - AI Accelerator Visionary

Black Sesame Technologies Inc; San Jose (CA); On-site; USD 250,000 - 320,000; Full time

Job summary

Black Sesame Technologies Inc seeks a Senior Principal NPU Architect to define the architecture of next‑generation AI accelerators for high‑performance autonomous driving NPU.

The role drives decisions across compute, memory hierarchy, interconnect, dataflow, and software co‑design, collaborating with compiler and algorithm teams to optimize performance, power, and scalability for CNNs, Transformers, multimodal models, and LLM inference.

Qualifications

• MS or PhD in EE, CE, CS, or related field.
• 8+ years of experience in NPU, GPU, CPU, ASIC, or computer architecture.
• Strong understanding of AI/ML workloads, memory systems, parallel processing, and performance optimization.
• Proven experience in architecture definition, modeling, and hardware/software co-design.
• Familiarity with low-precision computing and quantization, such as INT8, FP16, BF16, or FP8.
• Strong technical leadership and cross-functional communication skills.

Responsibilities

• Define NPU architecture and key design directions for compute, memory, interconnect, and execution model.
• Analyze AI workloads and translate them into architecture requirements and trade-offs.
• Drive architecture modeling, bottleneck analysis, and architecture exploration.
• Partner with compiler, runtime, and algorithm teams on hardware/software co-design.
• Guide architectural optimization for performance, power, area, and scalability.
• Work with RTL, verification, and software teams to ensure successful implementation.

Skills

NPU architecture

Hardware/software co-design

AI workloads

Memory systems design

Performance optimization

Cross-functional leadership

Education

MS or PhD in EE, CE, CS, or related field

Tools

RTL

Job description

Black Sesame Technologies Inc seeks a Senior Principal NPU Architect to define the architecture of next‑generation AI accelerators for high‑performance autonomous driving NPU.

The role drives decisions across compute, memory hierarchy, interconnect, dataflow, and software co‑design, collaborating with compiler and algorithm teams to optimize performance, power, and scalability for CNNs, Transformers, multimodal models, and LLM inference.