Senior ASIC Design Architect for AI Inference SoCs

Positron Corporation; Austin (TX); On-site; USD 225,000 - 350,000; Full time

Benefits offered by this job

Equity

Flexible work environment

Comprehensive benefits

Job summary

Positron AI is seeking a Principal ASIC Design Engineer to lead microarchitecture from concept through RTL signoff, mentoring junior engineers and driving PPA improvements across IP blocks and subsystems.

You will collaborate with architecture, verification, and physical design to deliver production-scale SystemVerilog RTL with robust interfaces, and you will own architectural tradeoffs that impact silicon performance and efficiency.

Qualifications

• 8+ years of ASIC/SoC RTL design experience.
• Proven track record leading designs from spec to signoff.

Responsibilities

• Define and document microarchitecture for complex IP blocks/subsystems.
• Deliver production-quality SystemVerilog RTL with well-defined interfaces and embedded assertions.
• Lead lint, CDC/RDC, DFT integration and synthesis bring-up.

Skills

SystemVerilog

RTL design

Leadership

PPA optimization

Synthesis/STA

DFT

Cross‑functional collaboration

Microarchitecture

Education

BS/MS in EE/CE

Tools

EDA tool suites

lint/CDC tools

Synthesis/STA tools

Cocotb/UVM

Job description

Positron AI is seeking a Principal ASIC Design Engineer to lead microarchitecture from concept through RTL signoff, mentoring junior engineers and driving PPA improvements across IP blocks and subsystems.

You will collaborate with architecture, verification, and physical design to deliver production-scale SystemVerilog RTL with robust interfaces, and you will own architectural tradeoffs that impact silicon performance and efficiency.