Senior Physical Design Verification Lead - CPU Blocks Tapeouts

TSMC - Taiwan Semiconductor Manufacturing Company Limited; San Jose (CA); On-site; USD 153,000 - 230,000; Full time

Job summary

TSMC Technology Inc. seeks a seasoned Physical Design Verification Lead to drive end‑to‑end verification for CPU blocks toward production tapeouts on N7 or below tech nodes. You will partner with the STA team and lead ECOs for tight timing closure, while addressing EM/Noise and Power/IR challenges.

You will supervise CTS and P&R strategies, optimize block floorplans, and mentor junior engineers, delivering silicon‑quality results at a customer site in the South Bay area.

Qualifications

• Master’s degree in Electrical, Computer Engineering, or Computer Science.
• 10–20 years in physical implementation and verification roles.
• Experience with EDA tools (Innovus/ICC2, Calibre) and design flows.
• Proven chip integration and sign‑off experience.

Responsibilities

• Lead end‑to‑end physical design verification for CPU blocks to tapeout.
• Collaborate with the STA team to implement ECOs for timing closure.
• Analyze and resolve Signal EM/Noise and Power/IR issues.
• Manage DRC, LVS, ERC and Antenna verifications and cleanups.
• Achieve final physical verification sign‑off across design metrics.
• Oversee CTS implementation and advanced P&R strategies.
• Optimize floorplans and design partitioning for quality.
• Provide technical leadership and mentorship to juniors.

Skills

EDA tools

Physical design verification

Scripting (TCL/Perl/Python)

Education

Master’s degree in Electrical/Computer Engineering or CS

Tools

Innovus/ICC2

Calibre

Job description

TSMC Technology Inc. seeks a seasoned Physical Design Verification Lead to drive end‑to‑end verification for CPU blocks toward production tapeouts on N7 or below tech nodes. You will partner with the STA team and lead ECOs for tight timing closure, while addressing EM/Noise and Power/IR challenges.

You will supervise CTS and P&R strategies, optimize block floorplans, and mentor junior engineers, delivering silicon‑quality results at a customer site in the South Bay area.