Senior Physical Design Lead — End-to-End Tapeout

Altera Corporation; San Jose (CA); Hybrid; USD 232.000 - 341.000; Vollzeit

Zusammenfassung

Altera Corporation in San Jose, California, seeks a Senior Physical Design Lead — Execution to drive day-to-day physical design execution from floorplan through tapeout, across blocks and full-chip integration. You will own the schedule and quality, coordinate across design teams, mentor engineers, and engage with senior customer stakeholders to resolve critical-path issues under schedule pressure.

Ideal candidates have 12–15+ years of PD experience on advanced nodes with multiple full-chip

Qualifikationen

• Bachelor's, Master's, or PhD in Electrical or Computer Engineering with 12–15+ years PD experience
• Minimum of four full-chip tapeouts at advanced nodes with execution ownership
• Proven track record delivering under schedule pressure without compromising quality
• Hands-on expertise across floorplanning, placement, clock-tree synthesis, routing, timing/power closure and signoff

Aufgaben

• Drive day-to-day physical design execution from floorplan to tapeout and cross-block integration
• Own schedule and quality for PD execution and mitigate risks early
• Coordinate execution across blocks and design teams to maintain full-chip closure
• Mentor PD engineers and influence best practices across teams
• Engage senior customers in technical discussions and reviews

Kenntnisse

Execution ownership

Schedule management

Cross-block coordination

Customer engagement

Mentorship

Scripting

Signoff knowledge

Ausbildung

Electrical/Computer Engineering degree

Tools

Synopsys Fusion Compiler

ICC2

PrimeTime

Cadence Innovus

Tempus

Voltus

Ansys RedHawk-SC

Calibre

Jobbeschreibung

Altera Corporation in San Jose, California, seeks a Senior Physical Design Lead — Execution to drive day-to-day physical design execution from floorplan through tapeout, across blocks and full-chip integration. You will own the schedule and quality, coordinate across design teams, mentor engineers, and engage with senior customer stakeholders to resolve critical-path issues under schedule pressure.

Ideal candidates have 12–15+ years of PD experience on advanced nodes with multiple full-chip