Senior Physical Design Lead: AI-Driven PnR & Signoff

191 Altera Corporation; San Jose (CA); On-site; USD 209,500 - 299,200; Full time

Job summary

Altera in San Jose, CA is seeking a Physical Design Technical Lead to own complex SOC and block‑level implementation end‑to‑end. You will drive floorplanning, power integrity, synthesis, place‑and‑route, CTS and ECO closure, while mentoring a small team of engineers across multiple tape‑out projects.

The role emphasizes cross‑functional collaboration with RTL, DFT, packaging and analog teams, and advancing ML/AI‑driven optimization in production flows to achieve tight timing, power and area

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of progressive experience in physical design or SoC backend.
• 4+ years in a technical lead, senior lead, or principal-level role with ownership.
• At least 3 successful tape-outs with ownership at 7nm or below.
• 5+ years of SoC-level floorplanning, top-level integration, and full-chip implementation.
• 10+ years with Synopsys Fusion Compiler and/or Cadence Innovus.
• 8+ years of static timing analysis and closure with PrimeTime.
• 5+ years of power integrity analysis and sign-off with RedHawk or Voltus.
• 5+ years of multi-voltage and low-power design methodologies (UPF/CPF).
• 5+ years of physical verification and sign-off with Calibre DRC/LVS (PVS exposure).
• 8+ years scripting in Tcl; 3+ years in Python/Perl.
• 2+ years evaluating ML/AI-driven PD tools; translating outputs to design actions.
• 2+ years Python-based data pipelines for design metrics.

Responsibilities

• Own floorplan architecture and power domain partitioning for large SOCs.
• Drive block-level implementation through synthesis, placement, CTS, and ECO closure.
• Lead cross-functional convergence on timing, power, and area targets across tape-outs.
• Collaborate with RTL, DFT, packaging, and analog teams to resolve integration challenges.
• Define and enforce physical design guidelines, constraints (SDC/UPF), and standards.
• Achieve signoff: STA, IR drop, electromigration, DRC/LVS, antenna.
• Drive PPA optimization: floorplanning, clock topology, routing resource planning.
• Lead critical-path analysis and timing-driven ECO resolution with teams.
• Manage hierarchy vs flat implementation flows and partitioning trade-offs.
• Champion ML/AI-based optimization in production PnR flows; integrate tools.
• Develop feedback loops between signoff results and ML training data pipelines.
• Present findings at design reviews and EDA forums; mentor 3–8 engineers.

Skills

Leadership

Mentoring

Tape-out experience

Scripting (Tcl/Python/Perl)

ML/AI PD knowledge

Education

Master’s degree in Electrical/Computer Engineering

Tools

Fusion Compiler

Innovus

Calibre DRC/LVS

PVS

PrimeTime

UPF/CPF

RedHawk

Voltus

Tcl scripting

Python scripting

Perl scripting

ML/AI PD tools

Job description

Altera in San Jose, CA is seeking a Physical Design Technical Lead to own complex SOC and block‑level implementation end‑to‑end. You will drive floorplanning, power integrity, synthesis, place‑and‑route, CTS and ECO closure, while mentoring a small team of engineers across multiple tape‑out projects.

The role emphasizes cross‑functional collaboration with RTL, DFT, packaging and analog teams, and advancing ML/AI‑driven optimization in production flows to achieve tight timing, power and area