Lead PD Verification for CPU Blocks & Tapeouts

TSMC - Taiwan Semiconductor Manufacturing Company Limited; California (MO); On-site; USD 153,000 - 230,000; Full time

Job summary

TSMC Technology Inc. is seeking a highly experienced Physical Design Verification Lead to drive end-to-end verification for CPU blocks on advanced N2/N7 nodes at a customer site in the South Bay area.

You will lead the verification flow, address timing, power, and parasitic challenges, and mentor junior engineers. You will collaborate with STA teams for ECOs, optimize CTS and Place & Route, and ensure successful production tapeouts with robust DRC/LVS/ERC checks.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
• 10–20 years hands-on physical implementation and verification experience.
• Proficiency with major EDA tools (Innovus/ICC2, Calibre) and established design flows.
• Extensive experience in chip integration and sign-off procedures.
• Experience with advanced nodes (TSMC N7 or below).
• Scripting in TCL, Perl, and Python for automation.

Responsibilities

• Lead end-to-end physical design verification for CPU blocks from block-level to production tapeout.
• Collaborate with STA team to implement ECOs for timing closure.
• Analyze and resolve Signal EM/Noise and Power IR/EM issues.
• Manage verification checks: DRC, LVS, ERC, and Antenna violations.
• Achieve final physical verification sign-off across design metrics.
• Oversee CTS implementation and advanced Place & Route strategies.
• Optimize floorplans and design partitioning.
• Provide technical leadership and mentorship to junior engineers.

Skills

Physical design verification

EDA tools

Scripting (TCL/Perl/Python)

Chip integration & sign-off

Customer-site work

Education

Master’s degree in Electrical/Computer Engineering or CS

Tools

Innovus

ICC2

Calibre

Job description

TSMC Technology Inc. is seeking a highly experienced Physical Design Verification Lead to drive end-to-end verification for CPU blocks on advanced N2/N7 nodes at a customer site in the South Bay area.

You will lead the verification flow, address timing, power, and parasitic challenges, and mentor junior engineers. You will collaborate with STA teams for ECOs, optimize CTS and Place & Route, and ensure successful production tapeouts with robust DRC/LVS/ERC checks.