Senior Physical Design & Verification Engineer

TSMC - Taiwan Semiconductor Manufacturing Company Limited; California (MO); Hybrid; USD 86,000 - 134,000; Full time

Job summary

TSMC - Taiwan Semiconductor Manufacturing Company Limited in San Jose, California, is seeking an Advanced Physical Design and Verification Engineer to lead DRC/LVS/antenna checks and fix PDV/EMIR/Noise/SigEM issues. The role includes timing ECOs on high-performance blocks and customizing clocks within a hybrid work setup.

You will report to the Manager of the Advanced Chip Implementation team and join a team driving cutting-edge semiconductor technology.

Qualifications

• Master’s degree required in Electrical Engineering or Computer Science.
• Strong knowledge of VLSI, digital ICs, and testability.
• Experience with RTL coding, physical implementation or design verification.
• Proficiency with major EDA tools and flows.

Responsibilities

• DRC/LVS/ERC/ANTENNA analysis and clean up
• Floorplan analysis and congestion solution
• PowerIR/EM analysis and fix
• Signal EM/Noise analysis and fix
• Physical verification sign off
• Implement ECOs for timing closure
• Customized Clock tree structure
• May also perform floorplan, place and route

Skills

VLSI design

Digital integrated circuits

Logic design

Design for testing

Computer architecture

Digital design automation

Python

Perl/TCL scripting

Education

Master’s degree in Electrical Engineering or Computer Science

Tools

EDA tools/design flows

Job description

TSMC - Taiwan Semiconductor Manufacturing Company Limited in San Jose, California, is seeking an Advanced Physical Design and Verification Engineer to lead DRC/LVS/antenna checks and fix PDV/EMIR/Noise/SigEM issues. The role includes timing ECOs on high-performance blocks and customizing clocks within a hybrid work setup.

You will report to the Manager of the Advanced Chip Implementation team and join a team driving cutting-edge semiconductor technology.