Senior Physical Design & Verification Engineer

TSMC; San Jose (CA); Hybrid; USD 86,000 - 134,000; Full time

Job summary

TSMC is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to lead DRC/LVS/ANTENNA checks, floorplan analysis, and timing ECOs for high-performance blocks. You will report to the Manager of Advanced Chip Implementation and join a team driving cutting-edge semiconductor design.

The role requires a Master’s in EE or CS, strong RTL/digital design experience, and hands-on use of major EDA tools. Hybrid schedule with 4 days in office in the South Bay area.

Qualifications

• Master’s degree in Electrical Engineering or Computer Science.
• Deep knowledge of hardware design including VLSI design, digital ICs, logic design, design for testing, computer architecture, and DDA.
• Experience in RTL coding, digital design and testing, physical implementation or design verification.
• In-depth knowledge of major EDA tools and design flows.
• Experience in Python and Perl/TCL language programming.
• Ability to work regularly at a customer site in the South Bay area.

Responsibilities

• DRC/LVS/ERC/ANTENNA analysis and clean up.
• Floorplan analysis and congestion solution.
• Power IR/EM analysis and fix.
• Signal EM/Noise analysis and fix.
• Physical verification sign off.
• Implement ECOs for timing closure.
• Customized Clock tree structure.
• May also perform floorplan, place and route.

Skills

RTL coding

Digital design

EDA tools

Python

Perl/TCL

Customer site work

Education

Master's degree in Electrical Engineering or Computer Science

Tools

EDA tools/flows

Job description

TSMC is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to lead DRC/LVS/ANTENNA checks, floorplan analysis, and timing ECOs for high-performance blocks. You will report to the Manager of Advanced Chip Implementation and join a team driving cutting-edge semiconductor design.

The role requires a Master’s in EE or CS, strong RTL/digital design experience, and hands-on use of major EDA tools. Hybrid schedule with 4 days in office in the South Bay area.