Advanced Physical Design & Verification Engineer – Hybrid

TSMC - Taiwan Semiconductor Manufacturing Company Limited; San Jose, Northern (CA, KY); Hybrid; USD 86,000 - 134,000; Full time

Benefits offered by this job

Hybrid work schedule

Competitive compensation

Job summary

TSMC Technology, Inc. is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to drive physical design checks and ECO-based timing closures.

The role involves DRC/LVS/EM analysis, floorplanning, and clock-tree customization in a hybrid work model with four days in office. The candidate should have a Master’s degree in electrical engineering or CS, strength in RTL, Python, and EDA tools, and a background in design verification or related internships.

Qualifications

• Master’s degree in Electrical Engineering or Computer Science is required or welcomed for fresh graduates.
• Experience with RTL design, digital design and testing, physical implementation or design verification is preferred.
• Proficiency in Python or Perl/TCL scripting and knowledge of major EDA tools/design flows required.

Responsibilities

• Conduct DRC/LVS/ANTENNA analysis and cleanup.
• Perform floorplan analysis and congestion solutions.
• Analyze Power/IR and signal EM for fixes.
• Perform physical verification sign-off and timing ECOs.
• Work on clock tree customization and possible floorplanning.

Skills

Python

Perl/TCL scripting

RTL coding

Education

Master’s degree in Electrical Engineering or Computer Science

Tools

EDA tools

Job description

TSMC Technology, Inc. is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to drive physical design checks and ECO-based timing closures.

The role involves DRC/LVS/EM analysis, floorplanning, and clock-tree customization in a hybrid work model with four days in office. The candidate should have a Master’s degree in electrical engineering or CS, strength in RTL, Python, and EDA tools, and a background in design verification or related internships.