Senior Physical Design Engineer — Tapeout to Signoff

Normal Computing Corporation; Palo Alto (CA); On-site; USD 210,000 - 260,000; Full time

Job summary

Normal Computing in Palo Alto is seeking a seasoned Physical Design Engineer to own the end-to-end silicon realization, from synthesis and floorplanning to timing signoff and GDSII tapeout.

You will collaborate with RTL, architecture, and DFT teams to push aggressive power, performance, and area targets while ensuring robust tapeout-proven execution across advanced nodes. The role demands a track record of tapeouts and hands-on backend expertise.

Qualifications

• Tapeout success across netlist-to-signoff is required.
• Deep hands-on experience with physical design flows and tooling.
• Strong problem-solving for STA, IR/EM, crosstalk, signoff issues.
• Experience collaborating with RTL/architecture/DFT teams.

Responsibilities

• Lead full netlist-to-GDSII physical design flow including floorplanning, P&R, CTS, and signoff.
• Own STA timing closure across corners and modes.
• Drive PPA optimization and ensure robust signoff and tapeout.
• Collaborate with RTL and architecture for early feasibility.

Skills

Tapeout track record

PD flow expertise

Backend debugging instincts

Cross-functional feasibility

Tools

Innovus

IC Compiler II

Tempus

PrimeTime

Pegasus

Calibre

Job description

Normal Computing in Palo Alto is seeking a seasoned Physical Design Engineer to own the end-to-end silicon realization, from synthesis and floorplanning to timing signoff and GDSII tapeout.

You will collaborate with RTL, architecture, and DFT teams to push aggressive power, performance, and area targets while ensuring robust tapeout-proven execution across advanced nodes. The role demands a track record of tapeouts and hands-on backend expertise.