Senior Physical Design Engineer – Tapeout & PPA Expert

Normal Computing Corp.; United States; On-site; USD 180,000 - 260,000; Full time

Job summary

Normal Computing Corp. is seeking a seasoned Physical Design Engineer to own the silicon realization path from synthesis and floorplanning to timing signoff and GDSII tapeout.

You will work alongside RTL and architecture teams to shape physical feasibility early in the cycle and drive backend flows to meet ambitious PPA targets. Responsibilities include leading CTS, P&R, STA, and signoff checks, optimizing for power, performance and area, and coordinating tapeout readiness and post-tapeout

Qualifications

• 3+ tapeouts from netlist to signoff across advanced technology nodes.
• Hands-on experience with PD tools and flow customization.
• Able to collaborate with RTL, architecture and DFT teams.
• Experience in AI or HPC chip startups a plus.
• Proficiency in TCL/Python scripting for PD flows.

Responsibilities

• Own end-to-end physical design flow from synthesis to GDSII tapeout.
• Optimize floorplanning, placement, CTS, P&R for best PPA.
• Lead STA timing constraints & signoff across corners.
• Drive DRC/LVS/ER C checks and antenna fixes.
• Collaborate with RTL/architecture/DFT teams for early feasibility.

Skills

Backend debugging

Floorplanning

P&R

CTS

STA

Signoff timing

Power integrity

DRC/LVS

Scripting (TCL/Python)

Tapeouts

Macro floorplanning

Cross-functional collaboration

Tools

Innovus

IC Compiler II

Tempus

PrimeTime

Pegasus

Calibre

Job description

Normal Computing Corp. is seeking a seasoned Physical Design Engineer to own the silicon realization path from synthesis and floorplanning to timing signoff and GDSII tapeout.

You will work alongside RTL and architecture teams to shape physical feasibility early in the cycle and drive backend flows to meet ambitious PPA targets. Responsibilities include leading CTS, P&R, STA, and signoff checks, optimizing for power, performance and area, and coordinating tapeout readiness and post-tapeout