Hardware Engineer (Physical Design)

Normal Computing Corp.; United States; On-site; USD 180,000 - 260,000; Full time

Job summary

Normal Computing Corp. is seeking a seasoned Physical Design Engineer to own the silicon realization path from synthesis and floorplanning to timing signoff and GDSII tapeout.

You will work alongside RTL and architecture teams to shape physical feasibility early in the cycle and drive backend flows to meet ambitious PPA targets. Responsibilities include leading CTS, P&R, STA, and signoff checks, optimizing for power, performance and area, and coordinating tapeout readiness and post-tapeout

Qualifications

• 3+ tapeouts from netlist to signoff across advanced technology nodes.
• Hands-on experience with PD tools and flow customization.
• Able to collaborate with RTL, architecture and DFT teams.
• Experience in AI or HPC chip startups a plus.
• Proficiency in TCL/Python scripting for PD flows.

Responsibilities

• Own end-to-end physical design flow from synthesis to GDSII tapeout.
• Optimize floorplanning, placement, CTS, P&R for best PPA.
• Lead STA timing constraints & signoff across corners.
• Drive DRC/LVS/ER C checks and antenna fixes.
• Collaborate with RTL/architecture/DFT teams for early feasibility.

Skills

Backend debugging

Floorplanning

P&R

CTS

STA

Signoff timing

Power integrity

DRC/LVS

Scripting (TCL/Python)

Tapeouts

Macro floorplanning

Cross-functional collaboration

Tools

Innovus

IC Compiler II

Tempus

PrimeTime

Pegasus

Calibre

Job description

• As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout
• Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams
• You’ll drive the full backend implementation flow-optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets
• Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R)
• Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes
• Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis
• Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry
• Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility
• Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed

We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven executionThe ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architecturesBackend Debugging Instincts: Strong problem-solving skills in analyzing & resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violationsPD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closureTapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodesCross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibilityExperience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cyclesExperience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration)Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows