Senior Physical Design Engineer: Tape-out & STA Expert

Wandata Tech; California; Sur place; USD 180 000 - 260 000; Plein temps

Résumé du poste

Wandata Tech in California is seeking an experienced ASIC/SoC Physical Design engineer to own end-to-end physical design activities from RTL to tape-out. You will oversee synthesis, STA, CTS, P&R, floorplanning, and timing closure while collaborating with IC Design and RTL teams to meet performance and area targets.

The role requires strong Cadence Innovus expertise, top-level floorplanning experience, and EM/IR analysis. A Bachelor's degree in EE/Electronics or a related field is required.

Qualifications

• Bachelor's degree required; relevant experience preferred.
• Experience with the physical design flow from RTL to tape-out.
• Proficiency with Cadence Innovus and standard EDA tools.
• Strong scripting using TCL or PERL.

Responsabilités

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS); manage clock trees and skew balancing.
• Perform floorplanning and layout activities; top-level floorplanning preferred.
• Contribute to flow and methodology development.
• Collaborate with IC Design and RTL Engineering teams.

Connaissances

RTL to Tape-out

Synthesis

STA

Timing Closure

Place & Route

CTS

Floorplanning

EM/IR Analysis

TCL/PERL scripting

Communication skills

Formation

Bachelor's Degree in Electrical Engineering/Electronics/related field

Outils

Cadence Innovus

EDA tools

Description du poste

Wandata Tech in California is seeking an experienced ASIC/SoC Physical Design engineer to own end-to-end physical design activities from RTL to tape-out. You will oversee synthesis, STA, CTS, P&R, floorplanning, and timing closure while collaborating with IC Design and RTL teams to meet performance and area targets.

The role requires strong Cadence Innovus expertise, top-level floorplanning experience, and EM/IR analysis. A Bachelor's degree in EE/Electronics or a related field is required.