Physical Design Engineer

Wandata Tech; California; On-site; USD 180,000 - 260,000; Full time

Job summary

Wandata Tech in California is seeking an experienced ASIC/SoC Physical Design engineer to own end-to-end physical design activities from RTL to tape-out. You will oversee synthesis, STA, CTS, P&R, floorplanning, and timing closure while collaborating with IC Design and RTL teams to meet performance and area targets.

The role requires strong Cadence Innovus expertise, top-level floorplanning experience, and EM/IR analysis. A Bachelor's degree in EE/Electronics or a related field is required.

Qualifications

• Bachelor's degree required; relevant experience preferred.
• Experience with the physical design flow from RTL to tape-out.
• Proficiency with Cadence Innovus and standard EDA tools.
• Strong scripting using TCL or PERL.

Responsibilities

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS); manage clock trees and skew balancing.
• Perform floorplanning and layout activities; top-level floorplanning preferred.
• Contribute to flow and methodology development.
• Collaborate with IC Design and RTL Engineering teams.

Skills

RTL to Tape-out

Synthesis

STA

Timing Closure

Place & Route

CTS

Floorplanning

EM/IR Analysis

TCL/PERL scripting

Communication skills

Education

Bachelor's Degree in Electrical Engineering/Electronics/related field

Tools

Cadence Innovus

EDA tools

Job description

Experience: 12+ Years

Key Responsibilities

• -Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• -Setup and synthesize RTL designs.
• -Perform timing closure using various methodologies and strategies, including top-level STA.
• -Conduct EM/IR analysis.
• -Execute Place & Route (P&R).
• -Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
• -Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.
• -Contribute to flow and methodology development.
• -Collaborate closely with IC Design and RTL Engineering teams.

Required Skills

• -Strong experience with Cadence Innovus.
• -Expertise in the complete Physical Design cycle from RTL to Tape-out.

Hands-on experience in:

• -Synthesis
• -Static Timing Analysis (STA)
• -Timing Closure
• -Place & Route
• -Clock Tree Synthesis (CTS)
• -Floorplanning
• -Physical Verification
• -EM/IR Analysis
• -Strong TCL and/or PERL scripting skills.
• -Proficiency with industry-standard EDA tools.
• -Excellent communication and collaboration skills.

Education

• -Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.

Preferred Profile

• -Deep expertise in top-level floorplanning and STA.
• -Proven success delivering complex ASIC/SoC designs through tape-out.