Senior Physical Design Engineer: Synthesis & Floorplanning

CORE Occupational Medicine; Sunnyvale (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

CORE Occupational Medicine is seeking an experienced Physical Design Engineer to join our silicon engineering team in the Sunnyvale/San Jose area. You will work on cutting-edge ASIC/SoC designs, driving RTL synthesis, timing optimization, and floorplanning to meet high performance, low power, and area goals.

Collaborate with RTL, architecture, verification, and physical design teams across the chip development lifecycle to ensure smooth convergence, provide actionable feedback, and support

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of ASIC/SoC physical design experience.
• Strong RTL synthesis and timing optimization expertise.
• Experience with floorplanning for modern technology nodes.
• Excellent cross-functional collaboration and communication skills.

Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals.
• Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution.
• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation.
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence.
• Support timing closure by identifying implementation bottlenecks and recommending design improvements.
• Participate in design reviews and contribute to continuous process and methodology improvements.

Job description

CORE Occupational Medicine is seeking an experienced Physical Design Engineer to join our silicon engineering team in the Sunnyvale/San Jose area. You will work on cutting-edge ASIC/SoC designs, driving RTL synthesis, timing optimization, and floorplanning to meet high performance, low power, and area goals.

Collaborate with RTL, architecture, verification, and physical design teams across the chip development lifecycle to ensure smooth convergence, provide actionable feedback, and support