Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI

Talent Groups; Sunnyvale (CA); Hybrid; USD 90,000 - 150,000; Full time

Job summary

An innovative firm is seeking a skilled Physical Design Engineer with a focus on ASICs, SoCs, and VLSI. This exciting role encompasses block-level and top-level physical design responsibilities, including floorplanning, placement optimization, clock tree synthesis, and power integrity analysis. The ideal candidate will have strong scripting abilities and experience in managing complex routing challenges. Join a dynamic team in a hybrid work environment, where your contributions will play a pivotal role in advancing cutting-edge technology solutions in the IT services sector.

Qualifications

• Strong scripting experience is essential for this role.
• Expertise in floorplanning and placement optimization is required.
• Experience with static timing analysis is crucial.

Responsibilities

• Define optimal floorplans and manage power grid placements.
• Design robust clock trees and ensure seamless integration of IP blocks.
• Perform final netlist-to-GDSII implementation and verification.

Skills

Scripting

Floorplanning

Placement Optimization

Clock Tree Synthesis

Routing

Timing Closure

Power Integrity Analysis

Job description

Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI

Physical Design Engineer-ASICs, SoCs, VLSI

Full time

Sunnyvale, CA

Job Description:

Key Responsibilities:

Block-Level Physical Design:

• Floorplanning & Partitioning – Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization – Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) – Design and optimize low-skew, high-performance clock networks.
• Routing & DRC Closure – Ensure successful global and detailed routing, meeting design rule constraints.
• Timing Closure – Work on setup/hold timing violations, signal integrity, and cross-talk reduction using static timing analysis (STA).
• Power & IR Drop Analysis – Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.

Top-Level Physical Design:

• Chip-Level Floorplanning & Hierarchical Design – Manage top-level layout planning, pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution – Design robust clock trees and power delivery networks (PDN).
• Integration of IP & Sub-blocks – Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off – Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
• DFT Integration – Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Information Technology

Industries

IT Services and IT Consulting