Senior Physical Design Engineer – RTL Synthesis & PPA

N2P Systems; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

N2P Systems in Sunnyvale, CA is seeking an experienced Physical Design Engineer to contribute to cutting-edge ASIC/SoC designs. You will drive RTL synthesis, timing optimization, and floorplanning across multi-disciplinary teams to meet performance, power, and area targets.

The role requires a strong background in physical design for advanced nodes, excellent collaboration skills, and a track record of delivering high-quality seed implementations in a fast-paced silicon organization.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in ASIC/SoC physical design.
• Expertise in RTL synthesis and timing optimization.
• Solid experience with floorplanning for advanced technology nodes.
• Strong understanding of netlist optimization and physical implementation methodologies.
• Experience collaborating with RTL/design teams to improve design quality and implementation efficiency.
• Excellent communication and cross-functional collaboration skills.

Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals.
• Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution.
• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation.
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence.
• Support timing closure by identifying implementation bottlenecks and recommending design improvements.
• Participate in design reviews and contribute to continuous process and methodology improvements.

Skills

RTL synthesis

Timing optimization

Floorplanning

Netlist optimization

Cross-functional collaboration

Communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

EDA tools

Job description

N2P Systems in Sunnyvale, CA is seeking an experienced Physical Design Engineer to contribute to cutting-edge ASIC/SoC designs. You will drive RTL synthesis, timing optimization, and floorplanning across multi-disciplinary teams to meet performance, power, and area targets.

The role requires a strong background in physical design for advanced nodes, excellent collaboration skills, and a track record of delivering high-quality seed implementations in a fast-paced silicon organization.