Physical Design Engineer

CORE Occupational Medicine; Sunnyvale (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

CORE Occupational Medicine is seeking an experienced Physical Design Engineer to join our silicon engineering team in the Sunnyvale/San Jose area. You will work on cutting-edge ASIC/SoC designs, driving RTL synthesis, timing optimization, and floorplanning to meet high performance, low power, and area goals.

Collaborate with RTL, architecture, verification, and physical design teams across the chip development lifecycle to ensure smooth convergence, provide actionable feedback, and support

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of ASIC/SoC physical design experience.
• Strong RTL synthesis and timing optimization expertise.
• Experience with floorplanning for modern technology nodes.
• Excellent cross-functional collaboration and communication skills.

Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals.
• Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution.
• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation.
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence.
• Support timing closure by identifying implementation bottlenecks and recommending design improvements.
• Participate in design reviews and contribute to continuous process and methodology improvements.

Job description

Job Title

Physical Design Engineer

Location

San Jose, CA

Job Description

Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization.

We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.

Key Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals
• Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution
• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence
• Support timing closure by identifying implementation bottlenecks and recommending design improvements
• Participate in design reviews and contribute to continuous process and methodology improvements

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• Strong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience.
• Expertise in RTL synthesis and timing optimization
• Solid experience with floorplanning for advanced technology nodes
• Strong understanding of netlist optimization and physical implementation methodologies
• Experience collaborating with RTL/design teams to improve design quality and implementation efficiency
• Excellent communication and cross-functional collaboration skills

Preferred Skills

• Experience with industry-standard EDA tools for synthesis and physical design
• Strong understanding of timing, congestion, power, and area optimization techniques
• Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus