Senior Physical Design Engineer

Sapien Engineering

California

On-site

USD 130,000 - 190,000

Full time

47 hours ago
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Job summary

Sapien Engineering is seeking a Senior Physical Design Engineer to join a leading global semiconductor company on a permanent basis. The role is full-time and based on-site in California, with locations in San Jose, San Diego, or Irvine.

The candidate will contribute to the full physical design cycle from RTL to tape-out, using Cadence Innovus and related flows. The ideal candidate will have 12+ years of physical design experience, proficiency in synthesis, STA, timing closure, P&R,

Qualifications

  • 12+ years of experience in physical design.
  • Full physical design cycle – RTL to tape-out.
  • Cadence Innovus
  • Synthesis, STA + timing closure, including top-level STA
  • Place & Route
  • Floorplanning – top-level floorplanning highly preferred
  • Physical verification + EM/IR analysis
  • TCL and/or PERL scripting
  • Flow and methodology development
  • Proven track record delivering complex ASIC/SoC designs through tape-out

Skills

12+ years experience
RTL to tape-out
Senior Physical Design

Education

Bachelor’s degree in Electrical/Electronics Engineering

Tools

Cadence Innovus
Synthesis
STA
Place & Route
Floorplanning
Physical verification
EM/IR analysis
TCL scripting
PERL scripting

Job description

Sapien Engineering are looking for a Senior Physical Design Engineer to join a leading global semiconductor company on a permanent basis.

This is a full-time role paying between $130,000 and $190,000 per annum, depending on experience.

The role is based on site in California at any of the following locations: San Jose, San Diego or Irvine.

Job requirements:

  • 12+ years’ experience in physical design
  • Full physical design cycle – RTL to tape-out
  • Cadence Innovus
  • Synthesis, STA + timing closure, including top-level STA
  • Place & Route
  • Floorplanning – top-level floorplanning highly preferred
  • Physical verification + EM/IR analysis
  • TCL and/or PERL scripting
  • Flow and methodology development
  • Proven track record delivering complex ASIC/SoC designs through tape-out
  • Bachelor’s degree in Electrical/Electronics Engineering or related field

Please note that all applicants must be US Citizens or Green Card holders.

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