Senior Physical Design Engineer: High-Performance IP

AMD; Santa Clara (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

AMD in Santa Clara seeks a collaborative Physical Design Engineer to drive RTL-to-GDS implementation for high-performance SerDes IP. You will contribute across synthesis, floorplanning, timing-driven place and route, clock tree synthesis, and sign-off, coordinating with distributed teams to deliver complex IP with high quality.

You will apply automated flows, analyze timing, power, and area, support design methodology, and push scalable engineering flows.

Qualifications

• Collaborative engineer with clear communication and technical curiosity.
• Analytical approach to balancing timing, power, area, and schedule.
• Able to prioritize work across multiple projects and teams.

Responsibilities

• Drive physical implementation of RTL blocks through synthesis, floorplanning, and signoff.
• Develop automated flows for clock tree synthesis, power gating, and related tasks.
• Analyze and optimize timing, power, and area targets.
• Support floorplanning and IP integration in complex designs.
• Perform and support timing, physical, and electrical checks.
• Collaborate with design teams to resolve timing challenges.
• Identify opportunities to improve automation and design methodologies.
• Support final signoff and delivery of large IP blocks.
• Learn and adapt to the team’s design environment early in the role.

Skills

Collaborative engineer

Clear communication

Analytical problem solving

Project prioritization

Tools

Verilog

EDA tools

Synthesis/Place & Route

Physical verification

Job description

AMD in Santa Clara seeks a collaborative Physical Design Engineer to drive RTL-to-GDS implementation for high-performance SerDes IP. You will contribute across synthesis, floorplanning, timing-driven place and route, clock tree synthesis, and sign-off, coordinating with distributed teams to deliver complex IP with high quality.

You will apply automated flows, analyze timing, power, and area, support design methodology, and push scalable engineering flows.