Senior Physical Design Engineer: PPA & Floorplanning

Prodapt ASIC services (Formerly Innovative Logic); Sunnyvale (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Prodapt’s ASIC Services in Sunnyvale, CA seeks a highly skilled Physical Design Engineer to join a high‑performing silicon engineering team. The role focuses on cutting‑edge ASIC/SoC designs and requires collaboration across RTL, verification and physical design teams throughout the chip lifecycle.

The candidate will drive RTL synthesis, floor planning, and timing optimization, supporting design reviews and process improvements in a onsite, fast‑paced environment.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in ASIC/SoC physical design.
• Expertise in RTL synthesis and timing optimization.
• Floor planning for complex ASIC/SoC designs.
• Strong netlist optimization and physical implementation understanding.
• Experience collaborating with RTL/design teams to improve design quality.

Responsibilities

• Drive RTL synthesis and optimization to meet performance, power, and area goals.
• Perform floor planning for complex ASIC/SoC designs with timing and power considerations.
• Collaborate with RTL design engineers to improve RTL quality and implementation results.
• Analyze netlists and optimize to improve design quality and efficiency.
• Work cross-functionally with architecture, RTL, verification and physical design teams.
• Support timing closure by identifying bottlenecks and proposing design improvements.
• Participate in design reviews and drive process improvements.

Skills

RTL synthesis

Timing optimization

Floor planning

Netlist optimization

Cross-functional collaboration

Communication

Education

Bachelors or Masters in EE/CE

Tools

EDA tools

Job description

Prodapt’s ASIC Services in Sunnyvale, CA seeks a highly skilled Physical Design Engineer to join a high‑performing silicon engineering team. The role focuses on cutting‑edge ASIC/SoC designs and requires collaboration across RTL, verification and physical design teams throughout the chip lifecycle.

The candidate will drive RTL synthesis, floor planning, and timing optimization, supporting design reviews and process improvements in a onsite, fast‑paced environment.