Senior Physical Design Engineer

Prodapt ASIC services (Formerly Innovative Logic); Sunnyvale (CA); Vor Ort; USD 140.000 - 210.000; Vollzeit

Zusammenfassung

Prodapt’s ASIC Services in Sunnyvale, CA seeks a highly skilled Physical Design Engineer to join a high‑performing silicon engineering team. The role focuses on cutting‑edge ASIC/SoC designs and requires collaboration across RTL, verification and physical design teams throughout the chip lifecycle.

The candidate will drive RTL synthesis, floor planning, and timing optimization, supporting design reviews and process improvements in a onsite, fast‑paced environment.

Qualifikationen

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in ASIC/SoC physical design.
• Expertise in RTL synthesis and timing optimization.
• Floor planning for complex ASIC/SoC designs.
• Strong netlist optimization and physical implementation understanding.
• Experience collaborating with RTL/design teams to improve design quality.

Aufgaben

• Drive RTL synthesis and optimization to meet performance, power, and area goals.
• Perform floor planning for complex ASIC/SoC designs with timing and power considerations.
• Collaborate with RTL design engineers to improve RTL quality and implementation results.
• Analyze netlists and optimize to improve design quality and efficiency.
• Work cross-functionally with architecture, RTL, verification and physical design teams.
• Support timing closure by identifying bottlenecks and proposing design improvements.
• Participate in design reviews and drive process improvements.

Kenntnisse

RTL synthesis

Timing optimization

Floor planning

Netlist optimization

Cross-functional collaboration

Communication

Ausbildung

Bachelors or Masters in EE/CE

Tools

EDA tools

Jobbeschreibung

Company Overview:

Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 5,000 technology and domain experts in 30+ countries. Prodapt is part of the 130‑year‑old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

Position Summary:

We are currently seeking a highly skilled and experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting‑edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle.

Work Location & Arrangement:

Sunnyvale, CA (Onsite), Weekly 5 days

Mode of Interview:

Two rounds of Video interview

Job Description:

Key Responsibilities:

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals.
• Perform floor planning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution.
• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation.
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency.
• Work cross‑functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence.
• Support timing closure by identifying implementation bottlenecks and recommending design improvements.
• Participate in design reviews and contribute to continuous process and methodology improvements.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong hands‑on experience in ASIC/SoC physical design with 10+ years of industry experience.
• Expertise in RTL synthesis and timing optimization.
• Solid experience with floor planning for advanced technology nodes.
• Strong understanding of netlist optimization and physical implementation methodologies.
• Experience collaborating with RTL/design teams to improve design quality and implementation efficiency.
• Excellent communication and cross‑functional collaboration skills.

Preferred Skills:

• Experience with industry‑standard EDA tools for synthesis and physical design.
• Strong understanding of timing, congestion, power, and area optimization techniques.
• Experience working on high‑performance CPU, GPU, AI/ML, or networking SoCs is a plus.