Senior Physical Design Engineer – SoC & Tapeout Focus

Qualcomm; Santa Clara (CA); On-site; USD 107,400 - 161,200; Full time

Job summary

Qualcomm Atheros, Inc. is seeking a physical design engineer to join our Connectivity SoC team.

You will contribute to the complete physical design flow for complex, high‑speed, low‑power designs, including floorplanning, placement, routing, and timing closure. Candidates should have 2+ years of PD experience with tapeout exposure, scripting in Python/Perl/TCL, and familiarity with Cadence Innovus and Synopsys Fusion Compiler.

Qualifications

• 2+ years in physical design for tiles/sub-system/SoC with tapeout exposure.
• Experience in floorplanning of macro cells and PNR workflows.
• Proficiency with Cadence Innovus or Synopsys Fusion Compiler.

Responsibilities

• Contribute to the complete physical design flow of complex, high‑speed, low‑power designs.
• Develop tiles-level, area-optimized P&R methods and low power strategies.
• Address timing, ECOs, DV/DFT constraints and formal verification.

Skills

PD (Physical Design)

Floorplanning

Place & Route

Timing Closure

DFT

Formal Verification

IR Drop

Physical Verification

Scripting (Python/Perl/TCL)

Linux/Unix shell

Education

Bachelor's degree in Science/Engineering or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PTSI

Job description

Qualcomm Atheros, Inc. is seeking a physical design engineer to join our Connectivity SoC team.

You will contribute to the complete physical design flow for complex, high‑speed, low‑power designs, including floorplanning, placement, routing, and timing closure. Candidates should have 2+ years of PD experience with tapeout exposure, scripting in Python/Perl/TCL, and familiarity with Cadence Innovus and Synopsys Fusion Compiler.