PD Engineer

Qualcomm; Santa Clara (CA); On-site; USD 107,400 - 161,200; Full time

Job summary

Qualcomm Atheros, Inc. is seeking a physical design engineer to join our Connectivity SoC team.

You will contribute to the complete physical design flow for complex, high‑speed, low‑power designs, including floorplanning, placement, routing, and timing closure. Candidates should have 2+ years of PD experience with tapeout exposure, scripting in Python/Perl/TCL, and familiarity with Cadence Innovus and Synopsys Fusion Compiler.

Qualifications

• 2+ years in physical design for tiles/sub-system/SoC with tapeout exposure.
• Experience in floorplanning of macro cells and PNR workflows.
• Proficiency with Cadence Innovus or Synopsys Fusion Compiler.

Responsibilities

• Contribute to the complete physical design flow of complex, high‑speed, low‑power designs.
• Develop tiles-level, area-optimized P&R methods and low power strategies.
• Address timing, ECOs, DV/DFT constraints and formal verification.

Skills

PD (Physical Design)

Floorplanning

Place & Route

Timing Closure

DFT

Formal Verification

IR Drop

Physical Verification

Scripting (Python/Perl/TCL)

Linux/Unix shell

Education

Bachelor's degree in Science/Engineering or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PTSI

Job description

Company: Qualcomm Atheros, Inc.

Job Area: Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm-Atheros, a.k.a. QCA (http://www.qualcomm.com/qca/) is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast‑paced Integrated Wireless Technology team, the role will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high‑speed, low‑power designs.

Responsibilities

Qualcomm’s Connectivity SoC organization is seeking candidates for physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state‑of‑the‑art tools and technologies.

• Tasks also involve the tiles level development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals.
• Additional responsibilities in this role involve the experience of
  • functional and test (DFT) mode constraints for place and route,
  • floorplanning, power planning,
  • IR drop analysis,
  • routing, timing optimization and closure,
  • implementing timing fixes and functional ECOs,
  • debugging and fixing physical violations and formal verification.
• The individual should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell.
• This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Required Skills and Experience

• 2+ years industry experience in the following areas
  • Tiles level or sub‑system level or SoC top level physical design with successful tapeout experience,
  • Floorplanning of macro cells,
  • Place & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler,
  • Timing closure (STA) experience in Synopsys PTSI,
  • Function ECO implementation,
  • Formal verification (FV) experience,
  • Power domain analysis (IR Drop/PDN) experience,
  • Physical verification (PV) experience.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field.

Equal Opportunity & Accessibility

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail [e-mail] or call Qualcomm's toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay Range and Other Compensation & Benefits

Pay range: $107,400.00 - $161,200.00. The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

If you would like more information about this role, please contact Qualcomm Careers.