Senior SoC Physical Design Engineer: Power & Timing

Qualcomm; Austin (TX); On-site; USD 124,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a candidate to independently plan and perform moderately-defined Physical Design responsibilities for high-speed DDR, graphics, and SOC flows.

The role focuses on optimizing power, performance, and methodology while supporting PDN and timing closure. Responsibilities include floor planning, clock tree synthesis, place-and-route, LVS/DRC checks, and cross-functional collaboration to drive tapeout readiness and signoff.

Qualifications

• Master's degree in Electrical Engineering or related field.
• Experience with physical design flows and methodology.
• Knowledge of LVS/DRC and design-for-manufacturing/yield checks.

Responsibilities

• Plan and perform physical design activities for high-speed DDR, graphics, and SOC flows.
• Conduct Floor Planning and Clock Tree Synthesis as part of PD design.
• Execute Place and Route steps and ensure PDN integrity.
• Perform timing analysis and closure to meet signoff targets.
• Support cross-functional engineering reviews and drive tapeout readiness.

Skills

Floor Planning

Clock Tree Synthesis

Place and Route

PDN

Timing analysis

Education

Master's Degree in Electrical Engineering

Job description

Qualcomm Technologies, Inc. is seeking a candidate to independently plan and perform moderately-defined Physical Design responsibilities for high-speed DDR, graphics, and SOC flows.

The role focuses on optimizing power, performance, and methodology while supporting PDN and timing closure. Responsibilities include floor planning, clock tree synthesis, place-and-route, LVS/DRC checks, and cross-functional collaboration to drive tapeout readiness and signoff.