Physical Design Engineer: High-Speed SoC & Power

Qualcomm

Santa Clara (CA)

On-site

USD 107,400 - 161,200

Full time

14 days+

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Job summary

Qualcomm Atheros, Inc. in Santa Clara, CA is seeking a Physical Design Engineer to join the Connectivity SoC team.

You will work on the complete physical design flow for high-speed, low-power designs, including floorplanning, place-and-route, power planning, IR drop analysis, timing closure, and ECOs. Proficiency with Python and shell scripting, and experience with Cadence Innovus or Synopsys Fusion Compiler is required.

Qualifications

  • 2+ years of PD experience with tapeout in tile/sub-system/SoC level.
  • Floorplanning of macro cells and macro placement.
  • Experience with P&R tools (Cadence Innovus and/or Fusion Compiler).
  • Timing closure (STA) and ECO implementation.
  • Formal verification and PV (physical verification) experience.
  • IR drop/power analysis and DV/DFT constraint handling.
  • Scripting in Python, Perl/TCL, and shell scripting.

Responsibilities

  • Deliver PD solutions from netlist and timing constraints to final product.
  • Handle floorplanning, power planning, IR drop analysis and routing.
  • Implement timing fixes and functional ECOs; debug physical violations.
  • Collaborate with design/verification teams and perform tapeout readiness.

Skills

Floorplanning
Placement & Routing
Timing closure
Power/IR drop analysis
DFT constraints
Python scripting
Shell scripting
Formal verification
Physical verification

Education

Bachelor's degree in Science/Engineering

Tools

Cadence Innovus
Synopsys Fusion Compiler
Synopsys PTSI
PV/STA tools

Job description

Qualcomm Atheros, Inc. in Santa Clara, CA is seeking a Physical Design Engineer to join the Connectivity SoC team.

You will work on the complete physical design flow for high-speed, low-power designs, including floorplanning, place-and-route, power planning, IR drop analysis, timing closure, and ECOs. Proficiency with Python and shell scripting, and experience with Cadence Innovus or Synopsys Fusion Compiler is required.

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