Physical Design Engineer- Senior

Qualcomm; Austin (TX); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus program

Opportunities for annual RSU grants

Collaborative team environment

Job summary

Qualcomm is seeking a talented Physical Design Engineer to join their DSP PD team in Austin, Texas. In this role, you'll innovate and implement DSP cores utilizing advanced tools. You will handle complete Physical Design flows, conduct PPA analysis, and manage tapeout activities to meet rigorous performance standards.

The ideal candidate will have a Bachelor’s or Master’s degree in Electrical Engineering and over 3 years of industry experience. Join Qualcomm to work on next-generation products within a collaborative environment focusing on technical excellence.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 3+ years of industry experience in Physical Design for ASIC/SoC.
• Proven tapeout experience with successful delivery of complex cores.

Responsibilities

• Own and execute complete Physical Design flow from netlist to GDSII.
• Perform PPA analysis and optimization to meet power, performance, and area targets.
• Manage tapeout activities, ensuring signoff for DRC, LVS, and timing.

Skills

Physical Design

DAC and Tools like Cadence Innovus

Scripting in Perl, TCL, Python

Timing Closure

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in related field

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

Synopsys PrimeTime

Job description

General Summary

QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state‑of‑the‑art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes. Backfill.

Key Responsibilities

• Own and execute complete Physical Design flow from netlist to GDSII:
  • Floorplanning, power planning, IR‑drop analysis
  • Placement, MMMC clock-tree synthesis, routing
  • Timing optimization and closure across multiple modes and corners
• Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
• Develop and enable low‑power implementation methods and customized P&R strategies for area reduction and performance improvement.
• Debug timing violations, implement timing fixes, and roll in functional ECOs.
• Conduct RC extraction, signal‑integrity, crosstalk noise/delay analysis, and formal verification.
• Manage tapeout activities, ensuring sign‑off for DRC, LVS, timing, power integrity, and reliability.
• Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
• Contribute to flow enhancements and automation using scripting (Perl/TCL, Python, Linux shell).

Minimum Qualifications

• Degree and experience:
  • Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 3+ years of industry experience in Physical Design for ASIC/SoC.
• Proven tapeout experience with successful delivery of complex cores.
• Hands‑on expertise with:
  • Place & Route tools: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler
  • Timing closure: Synopsys PrimeTime
  • Physical verification: DRC/LVS sign‑off flows
• Strong understanding of DFT, multi‑mode/multi‑corner designs, and ECO flows.
• Proficiency in scripting languages (Perl, TCL, Python) and Linux/Unix environments.

Preferred Skills

• Experience with latest advanced technology nodes.
• Knowledge of power integrity analysis (IR‑drop, EM) and low‑power design techniques.
• Familiarity with formal verification, understanding of DFM and post‑silicon validation.
• Ability to work in a fast‑paced environment and communicate effectively with cross‑functional teams.

Why Join Us?

• Work on cutting‑edge DSP cores for next‑generation products.
• Opportunity to lead tapeout and PPA optimization for high‑performance, low‑power designs.
• Collaborative team environment with strong focus on innovation and technical excellence.

Equal Opportunity Employer

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Accessibility and Accommodations

If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Please email disability‑[e-mail] or call Qualcomm’s toll‑free number for assistance.

Compensation

Pay range: $115,600.00 – $173,400.00. In addition, Qualcomm offers a competitive annual discretionary bonus program and opportunities for annual RSU grants.