Senior SoC Physical Design & Signoff Engineer

Qualcomm; Santa Clara (CA); On-site; USD 147,000 - 190,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA seeks a highly skilled engineer to drive physical design flow for high-performance SoCs including DDR and graphics paths.

You will optimize power, analyze PDN, and ensure timing closure to tapeout with cross-functional teams. The role requires a master's degree in Electrical/Computer Engineering or Computer Science and strong experience in floor planning, CTS, and LVS/DRC verification.

Qualifications

• Master's degree in Electrical or Computer Engineering or Computer Science.
• Experience in physical design flows for SoC.
• Familiarity with LVS/DRC and PDN design and timing closure.
• Strong collaboration and presentation in design reviews.

Responsibilities

• Plan and execute physical design flows for high-speed DDR, graphics, and SoC blocks.
• Perform floor planning, clock tree synthesis, placement and routing, and PDN analysis.
• Conduct timing analysis and closure to tapeout.
• Participate in design reviews and cross-functional meetings.

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA seeks a highly skilled engineer to drive physical design flow for high-performance SoCs including DDR and graphics paths.

You will optimize power, analyze PDN, and ensure timing closure to tapeout with cross-functional teams. The role requires a master's degree in Electrical/Computer Engineering or Computer Science and strong experience in floor planning, CTS, and LVS/DRC verification.