Application Specific Integrated Circuit Design Engineer

BayOne Solutions; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

BayOne Solutions is seeking a seasoned Physical Design Engineer to drive synthesis, PnR, and timing convergence for ASIC blocks onsite in San Jose, CA (with Austin, TX option).

You will collaborate with architects, RTL designers, and DFT engineers to ensure successful signoff, manage EM/IR, and push physical verification to closure while refining design flows and tooling.

Qualifications

• Bachelor's degree or equivalent in a technical field.
• 7+ years hands-on experience in physical design and implementation.
• Proficiency with Genus, Innovus, Tempus, and Quantus; deep understanding of physical design flows.

Responsibilities

• Execute synthesis, PNR, and STA for ASIC partitions with strict schedules.
• Collaborate with architects, RTL designers, and DFT engineers to resolve issues.
• Close EM/IR, drive LEC and physical verification signoff with methodology owners.
• Partner with design teams to identify and address physical design challenges.
• Refine implementation and physical design methodologies including EM/IR, PDN, and LEC.
• Troubleshoot flow issues and coordinate with EDA vendors to resolve them.

Skills

Synthesis

Place & Route (PnR)

Physical verification

Timing convergence

TCL scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Genus

Innovus

Tempus

Quantus

Job description

• Onsite in San Jose, CA. If you have candidate ready to work from our client office in Austin ,TX then please mention on resume , we will evaluate those resumes.
• We are looking for a CW similar to a Physical Design Engineer

Job Responsibilities:

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands‑on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
• Proficiency in utilizing Electronic Design Automation (EDA) tools such as Genus ,Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
• Genus ,Innovus are must have

Preferred Qualifications:

• 7+ years of experience in physical design roles and related activities.
• Proven ability to adhere to tight schedules and implement low‑power design techniques.
• Experience in System‑on‑Chip (SoC) design and implementation.
• Expertise in sub‑7nm node technologies.
• Familiarity with industry‑standard EDA tools and their capabilities.
• Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.